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sync code with last fixes and improvements from OpenBSD

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This commit is contained in:
purplerain 2023-07-20 23:56:46 +00:00
parent f57be82572
commit 58b04bcee7
Signed by: purplerain
GPG key ID: F42C07F07E2E35B7
468 changed files with 9958 additions and 7882 deletions
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7
sys/dev/dt/dt_dev.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: dt_dev.c,v 1.27 2023/06/28 08:23:25 claudio Exp $ */
/* $OpenBSD: dt_dev.c,v 1.28 2023/07/14 07:07:08 claudio Exp $ */
/*
* Copyright (c) 2019 Martin Pieuchot <mpi@openbsd.org>
@ -224,7 +224,6 @@ dtclose(dev_t dev, int flags, int mode, struct proc *p)
int
dtread(dev_t dev, struct uio *uio, int flags)
{
struct sleep_state sls;
struct dt_softc *sc;
struct dt_evt *estq;
struct dt_pcb *dp;
@ -240,8 +239,8 @@ dtread(dev_t dev, struct uio *uio, int flags)
return (EMSGSIZE);
while (!sc->ds_evtcnt) {
sleep_setup(&sls, sc, PWAIT | PCATCH, "dtread");
error = sleep_finish(&sls, PWAIT | PCATCH, 0, !sc->ds_evtcnt);
sleep_setup(sc, PWAIT | PCATCH, "dtread");
error = sleep_finish(0, !sc->ds_evtcnt);
if (error == EINTR || error == ERESTART)
break;
}

18
sys/dev/fdt/rkgpio.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: rkgpio.c,v 1.10 2023/03/05 14:45:07 patrick Exp $ */
/* $OpenBSD: rkgpio.c,v 1.11 2023/07/10 13:48:02 patrick Exp $ */
/*
* Copyright (c) 2017 Mark Kettenis <kettenis@openbsd.org>
* Copyright (c) 2019 Patrick Wildt <patrick@blueri.se>
@ -56,6 +56,9 @@
#define GPIO_INT_TYPE_H 0x0024
#define GPIO_INT_POLARITY_L 0x0028
#define GPIO_INT_POLARITY_H 0x002c
#define GPIO_INT_STATUS_V2 0x0050
#define GPIO_PORT_EOI_L 0x0060
#define GPIO_PORT_EOI_H 0x0064
#define GPIO_EXT_PORT 0x0070
#define GPIO_VER_ID 0x0078
#define GPIO_VER_ID_1_0 0x00000000
@ -276,7 +279,10 @@ rkgpio_intr(void *cookie)
uint32_t status, pending;
int pin, s;
status = HREAD4(sc, GPIO_INT_STATUS);
if (sc->sc_version == 2)
status = HREAD4(sc, GPIO_INT_STATUS_V2);
else
status = HREAD4(sc, GPIO_INT_STATUS);
pending = status;
while (pending) {
@ -292,7 +298,13 @@ rkgpio_intr(void *cookie)
pending &= ~(1 << pin);
}
HWRITE4(sc, GPIO_PORTS_EOI, status);
if (sc->sc_version == 2) {
HWRITE4(sc, GPIO_PORT_EOI_L,
(status & 0xffff) << 16 | (status & 0xffff));
HWRITE4(sc, GPIO_PORT_EOI_H,
status >> 16 | (status & 0xffff0000));
} else
HWRITE4(sc, GPIO_PORTS_EOI, status);
return 1;
}

14
sys/dev/fdt/rkpciephy.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: rkpciephy.c,v 1.2 2023/07/08 09:12:28 patrick Exp $ */
/* $OpenBSD: rkpciephy.c,v 1.3 2023/07/09 19:11:30 patrick Exp $ */
/*
* Copyright (c) 2023 Mark Kettenis <kettenis@openbsd.org>
*
@ -202,18 +202,16 @@ rk3588_pciephy_enable(void *cookie, uint32_t *cells)
}
regmap_write_4(phy, RK3588_PCIE3PHY_GRF_CMN_CON(0), reg);
grf = OF_getpropint(node, "rockchip,phy-grf", 0);
grf = OF_getpropint(node, "rockchip,pipe-grf", 0);
pipe = regmap_byphandle(grf);
if (pipe != NULL) {
reg = RK3588_PHP_GRF_PCIE0L0_MASK | RK3588_PHP_GRF_PCIE0L1_MASK;
/* If lane 1 is configured, move it from Combo to PCIE3 PHY */
if (num_lanes >= 2 && data_lanes[1] != 0) {
/* If lane 1 goes to PCIe3_1L0, move from Combo to PCIE3 PHY */
if (num_lanes >= 2 && data_lanes[1] == 2)
reg |= RK3588_PHP_GRF_PCIE0L0_PCIE3;
}
/* If lane 3 is configured, move it from Combo to PCIE3 PHY */
if (num_lanes >= 4 && data_lanes[3] != 0) {
/* If lane 3 goes to PCIe3_1L1, move from Combo to PCIE3 PHY */
if (num_lanes >= 4 && data_lanes[3] == 4)
reg |= RK3588_PHP_GRF_PCIE0L1_PCIE3;
}
regmap_write_4(pipe, RK3588_PHP_GRF_PCIESEL_CON, reg);
}

44
sys/dev/fdt/tascodec.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: tascodec.c,v 1.6 2023/02/04 20:04:20 kettenis Exp $ */
/* $OpenBSD: tascodec.c,v 1.7 2023/07/15 13:35:17 kettenis Exp $ */
/*
* Copyright (c) 2022 Mark Kettenis <kettenis@openbsd.org>
*
@ -35,6 +35,7 @@
#define PWR_CTL 0x02
#define PWR_CTL_ISNS_PD (1 << 3)
#define PWR_CTL_VSNS_PD (1 << 2)
#define PWR_CTL_MODE_MASK (3 << 0)
#define PWR_CTL_MODE_ACTIVE (0 << 0)
#define PWR_CTL_MODE_MUTE (1 << 0)
#define PWR_CTL_MODE_SHUTDOWN (2 << 0)
@ -66,6 +67,7 @@ struct tascodec_softc {
struct dai_device sc_dai;
uint8_t sc_dvc;
uint8_t sc_mute;
};
int tascodec_match(struct device *, void *, void *);
@ -138,6 +140,7 @@ tascodec_attach(struct device *parent, struct device *self, void *aux)
/* Set volume to a reasonable level. */
sc->sc_dvc = PB_CFG2_DVC_PCM_30DB;
sc->sc_mute = PWR_CTL_MODE_ACTIVE;
tascodec_write(sc, PB_CFG2, sc->sc_dvc);
/* Default to stereo downmix mode for now. */
@ -244,6 +247,7 @@ tascodec_set_tdm_slot(void *cookie, int slot)
*/
enum {
TASCODEC_MASTER_VOL,
TASCODEC_MASTER_MUTE,
TASCODEC_OUTPUT_CLASS
};
@ -252,6 +256,7 @@ tascodec_set_port(void *priv, mixer_ctrl_t *mc)
{
struct tascodec_softc *sc = priv;
u_char level;
uint8_t mode;
switch (mc->dev) {
case TASCODEC_MASTER_VOL:
@ -259,6 +264,19 @@ tascodec_set_port(void *priv, mixer_ctrl_t *mc)
sc->sc_dvc = (PB_CFG2_DVC_PCM_MIN * (255 - level)) / 255;
tascodec_write(sc, PB_CFG2, sc->sc_dvc);
return 0;
case TASCODEC_MASTER_MUTE:
sc->sc_mute = mc->un.ord ?
PWR_CTL_MODE_MUTE : PWR_CTL_MODE_ACTIVE;
mode = tascodec_read(sc, PWR_CTL);
if ((mode & PWR_CTL_MODE_MASK) == PWR_CTL_MODE_ACTIVE ||
(mode & PWR_CTL_MODE_MASK) == PWR_CTL_MODE_MUTE) {
mode &= ~PWR_CTL_MODE_MASK;
mode |= sc->sc_mute;
tascodec_write(sc, PWR_CTL, mode);
}
return 0;
}
return EINVAL;
@ -276,6 +294,10 @@ tascodec_get_port(void *priv, mixer_ctrl_t *mc)
level = 255 - ((255 * sc->sc_dvc) / PB_CFG2_DVC_PCM_MIN);
mc->un.value.level[AUDIO_MIXER_LEVEL_MONO] = level;
return 0;
case TASCODEC_MASTER_MUTE:
mc->un.ord = (sc->sc_mute == PWR_CTL_MODE_MUTE);
return 0;
}
return EINVAL;
@ -287,7 +309,8 @@ tascodec_query_devinfo(void *priv, mixer_devinfo_t *di)
switch (di->index) {
case TASCODEC_MASTER_VOL:
di->mixer_class = TASCODEC_OUTPUT_CLASS;
di->next = di->prev = AUDIO_MIXER_LAST;
di->prev = AUDIO_MIXER_LAST;
di->next = TASCODEC_MASTER_MUTE;
strlcpy(di->label.name, AudioNmaster, sizeof(di->label.name));
di->type = AUDIO_MIXER_VALUE;
di->un.v.num_channels = 1;
@ -295,6 +318,21 @@ tascodec_query_devinfo(void *priv, mixer_devinfo_t *di)
sizeof(di->un.v.units.name));
return 0;
case TASCODEC_MASTER_MUTE:
di->mixer_class = TASCODEC_OUTPUT_CLASS;
di->prev = TASCODEC_MASTER_VOL;
di->next = AUDIO_MIXER_LAST;
strlcpy(di->label.name, AudioNmute, sizeof(di->label.name));
di->type = AUDIO_MIXER_ENUM;
di->un.e.num_mem = 2;
di->un.e.member[0].ord = 0;
strlcpy(di->un.e.member[0].label.name, AudioNoff,
MAX_AUDIO_DEV_LEN);
di->un.e.member[1].ord = 1;
strlcpy(di->un.e.member[1].label.name, AudioNon,
MAX_AUDIO_DEV_LEN);
return 0;
case TASCODEC_OUTPUT_CLASS:
di->mixer_class = TASCODEC_OUTPUT_CLASS;
di->next = di->prev = AUDIO_MIXER_LAST;
@ -313,7 +351,7 @@ tascodec_trigger_output(void *cookie, void *start, void *end, int blksize,
struct tascodec_softc *sc = cookie;
tascodec_write(sc, PWR_CTL,
PWR_CTL_ISNS_PD | PWR_CTL_VSNS_PD | PWR_CTL_MODE_ACTIVE);
PWR_CTL_ISNS_PD | PWR_CTL_VSNS_PD | sc->sc_mute);
return 0;
}

121
sys/dev/fdt/tipd.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: tipd.c,v 1.1 2022/12/12 19:18:25 kettenis Exp $ */
/* $OpenBSD: tipd.c,v 1.2 2023/07/17 17:50:22 kettenis Exp $ */
/*
* Copyright (c) 2022 Mark Kettenis <kettenis@openbsd.org>
*
@ -29,6 +29,8 @@
#include <dev/i2c/i2cvar.h>
#define TPS_CMD1 0x08
#define TPS_DATA1 0x09
#define TPS_INT_EVENT_1 0x14
#define TPS_INT_EVENT_2 0x15
#define TPS_INT_MASK_1 0x16
@ -37,6 +39,11 @@
#define TPS_INT_CLEAR_2 0x19
#define TPS_STATUS 0x1a
#define TPS_STATUS_PLUG_PRESENT (1 << 0)
#define TPS_SYSTEM_POWER_STATE 0x20
#define TPS_SYSTEM_POWER_STATE_S0 0
#define TPS_SYSTEM_POWER_STATE_S5 5
#define TPS_CMD(s) ((s[3] << 24) | (s[2] << 16) | (s[1] << 8) | s[0])
/*
* Interrupt bits on the CD321x controllers used by Apple differ from
@ -56,9 +63,11 @@ struct tipd_softc {
int tipd_match(struct device *, void *, void *);
void tipd_attach(struct device *, struct device *, void *);
int tipd_activate(struct device *, int);
const struct cfattach tipd_ca = {
sizeof(struct tipd_softc), tipd_match, tipd_attach
sizeof(struct tipd_softc), tipd_match, tipd_attach, NULL,
tipd_activate
};
struct cfdriver tipd_cd = {
@ -69,7 +78,10 @@ int tipd_intr(void *);
int tipd_read_4(struct tipd_softc *, uint8_t, uint32_t *);
int tipd_read_8(struct tipd_softc *, uint8_t, uint64_t *);
int tipd_write_4(struct tipd_softc *, uint8_t, uint32_t);
int tipd_write_8(struct tipd_softc *, uint8_t, uint64_t);
int tipd_exec(struct tipd_softc *, const char *,
const void *, size_t, void *, size_t);
int
tipd_match(struct device *parent, void *match, void *aux)
@ -107,6 +119,31 @@ tipd_attach(struct device *parent, struct device *self, void *aux)
}
}
int
tipd_activate(struct device *self, int act)
{
struct tipd_softc *sc = (struct tipd_softc *)self;
uint8_t state;
int error;
switch (act) {
case DVACT_SUSPEND:
state = TPS_SYSTEM_POWER_STATE_S5;
error = tipd_exec(sc, "SSPS", &state, sizeof(state), NULL, 0);
if (error)
printf("%s: powerdown failed\n", sc->sc_dev.dv_xname);
break;
case DVACT_RESUME:
state = TPS_SYSTEM_POWER_STATE_S0;
error = tipd_exec(sc, "SSPS", &state, sizeof(state), NULL, 0);
if (error)
printf("%s: powerup failed\n", sc->sc_dev.dv_xname);
break;
}
return 0;
}
void
tipd_connect(struct tipd_softc *sc)
{
@ -206,6 +243,23 @@ tipd_read_8(struct tipd_softc *sc, uint8_t reg, uint64_t *val)
return error;
}
int
tipd_write_4(struct tipd_softc *sc, uint8_t reg, uint32_t val)
{
uint8_t buf[5];
int error;
buf[0] = 4;
htolem32(&buf[1], val);
iic_acquire_bus(sc->sc_tag, 0);
error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP,
sc->sc_addr, &reg, sizeof(reg), buf, sizeof(buf), 0);
iic_release_bus(sc->sc_tag, 0);
return error;
}
int
tipd_write_8(struct tipd_softc *sc, uint8_t reg, uint64_t val)
{
@ -222,3 +276,66 @@ tipd_write_8(struct tipd_softc *sc, uint8_t reg, uint64_t val)
return error;
}
int
tipd_exec(struct tipd_softc *sc, const char *cmd, const void *wbuf,
size_t wlen, void *rbuf, size_t rlen)
{
char buf[65];
uint32_t val;
int timo, error;
uint8_t reg = TPS_DATA1;
if (wlen >= sizeof(buf) - 1)
return EINVAL;
error = tipd_read_4(sc, TPS_CMD1, &val);
if (error)
return error;
if (val == TPS_CMD("!CMD"))
return EBUSY;
if (wlen > 0) {
buf[0] = wlen;
memcpy(&buf[1], wbuf, wlen);
iic_acquire_bus(sc->sc_tag, 0);
error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP,
sc->sc_addr, &reg, sizeof(reg), buf, sizeof(buf), 0);
iic_release_bus(sc->sc_tag, 0);
if (error)
return error;
}
error = tipd_write_4(sc, TPS_CMD1, TPS_CMD(cmd));
if (error)
return error;
for (timo = 1000; timo > 0; timo--) {
error = tipd_read_4(sc, TPS_CMD1, &val);
if (error)
return error;
if (val == TPS_CMD("!CMD"))
return EBUSY;
if (val == 0)
break;
delay(10);
}
if (timo == 0)
return ETIMEDOUT;
if (rlen > 0) {
memset(buf, 0, sizeof(buf));
iic_acquire_bus(sc->sc_tag, 0);
error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP,
sc->sc_addr, &reg, sizeof(reg), buf, sizeof(buf), 0);
iic_release_bus(sc->sc_tag, 0);
if (error)
return error;
if (buf[0] < rlen)
return EIO;
memcpy(rbuf, &buf[1], rlen);
}
return 0;
}

6
sys/dev/ic/aac.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: aac.c,v 1.94 2022/04/16 19:19:58 naddy Exp $ */
/* $OpenBSD: aac.c,v 1.95 2023/07/13 07:31:12 jsg Exp $ */
/*-
* Copyright (c) 2000 Michael Smith
@ -2074,9 +2074,7 @@ aac_rkt_set_interrupts(struct aac_softc *sc, int enable)
}
void
aac_eval_mapping(size, cyls, heads, secs)
u_int32_t size;
int *cyls, *heads, *secs;
aac_eval_mapping(u_int32_t size, int *cyls, int *heads, int *secs)
{
*cyls = size / AAC_HEADS / AAC_SECS;
if (*cyls < AAC_MAXCYLS) {

16
sys/dev/ic/aacvar.h
View file

@ -1,4 +1,4 @@
/* $OpenBSD: aacvar.h,v 1.16 2022/01/09 05:42:37 jsg Exp $ */
/* $OpenBSD: aacvar.h,v 1.17 2023/07/13 07:31:12 jsg Exp $ */
/*-
* Copyright (c) 2000 Michael Smith
@ -429,31 +429,25 @@ int aac_intr(void *);
/* These all require correctly aligned buffers */
static __inline__ void
aac_enc16(addr, value)
u_int8_t *addr;
u_int16_t value;
aac_enc16(u_int8_t *addr, u_int16_t value)
{
*(u_int16_t *)addr = htole16(value);
}
static __inline__ void
aac_enc32(addr, value)
u_int8_t *addr;
u_int32_t value;
aac_enc32(u_int8_t *addr, u_int32_t value)
{
*(u_int32_t *)addr = htole32(value);
}
static __inline__ u_int16_t
aac_dec16(addr)
u_int8_t *addr;
aac_dec16(u_int8_t *addr)
{
return letoh16(*(u_int16_t *)addr);
}
static __inline__ u_int32_t
aac_dec32(addr)
u_int8_t *addr;
aac_dec32(u_int8_t *addr)
{
return letoh32(*(u_int32_t *)addr);
}

11
sys/dev/pci/aac_pci.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: aac_pci.c,v 1.26 2022/03/11 18:00:45 mpi Exp $ */
/* $OpenBSD: aac_pci.c,v 1.27 2023/07/13 07:31:12 jsg Exp $ */
/*-
* Copyright (c) 2000 Michael Smith
@ -202,10 +202,7 @@ const struct cfattach aac_pci_ca = {
* Determine whether this is one of our supported adapters.
*/
int
aac_pci_probe(parent, match, aux)
struct device *parent;
void *match;
void *aux;
aac_pci_probe(struct device *parent, void *match, void *aux)
{
struct pci_attach_args *pa = aux;
struct aac_ident *m;
@ -224,9 +221,7 @@ aac_pci_probe(parent, match, aux)
}
void
aac_pci_attach(parent, self, aux)
struct device *parent, *self;
void *aux;
aac_pci_attach(struct device *parent, struct device *self, void *aux)
{
struct pci_attach_args *pa = aux;
pci_chipset_tag_t pc = pa->pa_pc;

11
sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c
View file

@ -129,9 +129,6 @@ static int amdgpu_cs_p1_user_fence(struct amdgpu_cs_parser *p,
bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
p->uf_entry.priority = 0;
p->uf_entry.tv.bo = &bo->tbo;
/* One for TTM and two for the CS job */
p->uf_entry.tv.num_shared = 3;
drm_gem_object_put(gobj);
size = amdgpu_bo_size(bo);
@ -885,15 +882,19 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
mutex_lock(&p->bo_list->bo_list_mutex);
/* One for TTM and one for the CS job */
/* One for TTM and one for each CS job */
amdgpu_bo_list_for_each_entry(e, p->bo_list)
e->tv.num_shared = 2;
e->tv.num_shared = 1 + p->gang_size;
p->uf_entry.tv.num_shared = 1 + p->gang_size;
amdgpu_bo_list_get_list(p->bo_list, &p->validated);
INIT_LIST_HEAD(&duplicates);
amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);
/* Two for VM updates, one for TTM and one for each CS job */
p->vm_pd.tv.num_shared = 3 + p->gang_size;
if (p->uf_entry.tv.bo && !ttm_to_amdgpu_bo(p->uf_entry.tv.bo)->parent)
list_add(&p->uf_entry.tv.head, &p->validated);

2
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
View file

@ -1972,6 +1972,8 @@ static int psp_securedisplay_initialize(struct psp_context *psp)
psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status);
dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n",
securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret);
/* don't try again */
psp->securedisplay_context.context.bin_desc.size_bytes = 0;
}
return 0;

3
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
View file

@ -170,8 +170,7 @@ static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t addre
memset(&err_rec, 0x0, sizeof(struct eeprom_table_record));
err_data.err_addr = &err_rec;
amdgpu_umc_fill_error_record(&err_data, address,
(address >> AMDGPU_GPU_PAGE_SHIFT), 0, 0);
amdgpu_umc_fill_error_record(&err_data, address, address, 0, 0);
if (amdgpu_bad_page_threshold != 0) {
amdgpu_ras_add_bad_pages(adev, err_data.err_addr,

16
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
View file

@ -1489,14 +1489,14 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
uint64_t eaddr;
/* validate the parameters */
if (saddr & ~LINUX_PAGE_MASK || offset & ~LINUX_PAGE_MASK ||
size == 0 || size & ~LINUX_PAGE_MASK)
if (saddr & ~LINUX_PAGE_MASK || offset & ~LINUX_PAGE_MASK || size & ~LINUX_PAGE_MASK)
return -EINVAL;
if (saddr + size <= saddr || offset + size <= offset)
return -EINVAL;
/* make sure object fit at this offset */
eaddr = saddr + size - 1;
if (saddr >= eaddr ||
(bo && offset + size > amdgpu_bo_size(bo)) ||
if ((bo && offset + size > amdgpu_bo_size(bo)) ||
(eaddr >= adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT))
return -EINVAL;
@ -1555,14 +1555,14 @@ int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
int r;
/* validate the parameters */
if (saddr & ~LINUX_PAGE_MASK || offset & ~LINUX_PAGE_MASK ||
size == 0 || size & ~LINUX_PAGE_MASK)
if (saddr & ~LINUX_PAGE_MASK || offset & ~LINUX_PAGE_MASK || size & ~LINUX_PAGE_MASK)
return -EINVAL;
if (saddr + size <= saddr || offset + size <= offset)
return -EINVAL;
/* make sure object fit at this offset */
eaddr = saddr + size - 1;
if (saddr >= eaddr ||
(bo && offset + size > amdgpu_bo_size(bo)) ||
if ((bo && offset + size > amdgpu_bo_size(bo)) ||
(eaddr >= adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT))
return -EINVAL;

13
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c
View file

@ -115,18 +115,19 @@ static struct kfd_mem_obj *allocate_mqd(struct kfd_dev *kfd,
&(mqd_mem_obj->gtt_mem),
&(mqd_mem_obj->gpu_addr),
(void *)&(mqd_mem_obj->cpu_ptr), true);
if (retval) {
kfree(mqd_mem_obj);
return NULL;
}
} else {
retval = kfd_gtt_sa_allocate(kfd, sizeof(struct v9_mqd),
&mqd_mem_obj);
}
if (retval) {
kfree(mqd_mem_obj);
return NULL;
if (retval)
return NULL;
}
return mqd_mem_obj;
}
static void init_mqd(struct mqd_manager *mm, void **mqd,

10
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
View file

@ -6974,13 +6974,7 @@ static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
drm_add_modes_noedid(connector, 640, 480);
} else {
amdgpu_dm_connector_ddc_get_modes(connector, edid);
/* most eDP supports only timings from its edid,
* usually only detailed timings are available
* from eDP edid. timings which are not from edid
* may damage eDP
*/
if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
amdgpu_dm_connector_add_common_modes(encoder, connector);
amdgpu_dm_connector_add_common_modes(encoder, connector);
amdgpu_dm_connector_add_freesync_modes(connector, edid);
}
amdgpu_dm_fbc_init(connector);
@ -8877,6 +8871,8 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
/* Now check if we should set freesync video mode */
if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream &&
dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream) &&
is_timing_unchanged_for_freesync(new_crtc_state,
old_crtc_state)) {
new_crtc_state->mode_changed = false;

3
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
View file

@ -312,6 +312,9 @@ void dcn30_smu_set_display_refresh_from_mall(struct clk_mgr_internal *clk_mgr, b
/* bits 8:7 for cache timer scale, bits 6:1 for cache timer delay, bit 0 = 1 for enable, = 0 for disable */
uint32_t param = (cache_timer_scale << 7) | (cache_timer_delay << 1) | (enable ? 1 : 0);
smu_print("SMU Set display refresh from mall: enable = %d, cache_timer_delay = %d, cache_timer_scale = %d\n",
enable, cache_timer_delay, cache_timer_scale);
dcn30_smu_send_msg_with_param(clk_mgr,
DALSMC_MSG_SetDisplayRefreshFromMall, param, NULL);
}

3
sys/dev/pci/drm/amd/display/dc/core/amdgpu_dc.c
View file

@ -2360,9 +2360,6 @@ static enum surface_update_type det_surface_update(const struct dc *dc,
enum surface_update_type overall_type = UPDATE_TYPE_FAST;
union surface_update_flags *update_flags = &u->surface->update_flags;
if (u->flip_addr)
update_flags->bits.addr_update = 1;
if (!is_surface_in_context(context, u->surface) || u->surface->force_full_update) {
update_flags->raw = 0xFFFFFFFF;
return UPDATE_TYPE_FULL;

2
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
View file

@ -810,7 +810,7 @@ static bool CalculatePrefetchSchedule(
*swath_width_chroma_ub = dml_ceil(SwathWidthY / 2 - 1, myPipe->BlockWidth256BytesC) + myPipe->BlockWidth256BytesC;
} else {
*swath_width_luma_ub = dml_ceil(SwathWidthY - 1, myPipe->BlockHeight256BytesY) + myPipe->BlockHeight256BytesY;
if (myPipe->BlockWidth256BytesC > 0)
if (myPipe->BlockHeight256BytesC > 0)
*swath_width_chroma_ub = dml_ceil(SwathWidthY / 2 - 1, myPipe->BlockHeight256BytesC) + myPipe->BlockHeight256BytesC;
}

2
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
View file

@ -116,7 +116,7 @@ void dml32_rq_dlg_get_rq_reg(display_rq_regs_st *rq_regs,
else
rq_regs->rq_regs_l.min_meta_chunk_size = dml_log2(min_meta_chunk_bytes) - 6 + 1;
if (min_meta_chunk_bytes == 0)
if (p1_min_meta_chunk_bytes == 0)
rq_regs->rq_regs_c.min_meta_chunk_size = 0;
else
rq_regs->rq_regs_c.min_meta_chunk_size = dml_log2(p1_min_meta_chunk_bytes) - 6 + 1;

18
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
View file

@ -431,7 +431,13 @@ static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
{
struct atom_smc_dpm_info_v4_9 *smc_dpm_table;
int index, ret;
I2cControllerConfig_t *table_member;
PPTable_beige_goby_t *ppt_beige_goby;
PPTable_t *ppt;
if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))
ppt_beige_goby = smu->smu_table.driver_pptable;
else
ppt = smu->smu_table.driver_pptable;
index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
smc_dpm_info);
@ -440,9 +446,13 @@ static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
(uint8_t **)&smc_dpm_table);
if (ret)
return ret;
GET_PPTABLE_MEMBER(I2cControllers, &table_member);
memcpy(table_member, smc_dpm_table->I2cControllers,
sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header));
if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))
smu_memcpy_trailing(ppt_beige_goby, I2cControllers, BoardReserved,
smc_dpm_table, I2cControllers);
else
smu_memcpy_trailing(ppt, I2cControllers, BoardReserved,
smc_dpm_table, I2cControllers);
return 0;
}

2
sys/dev/pci/drm/display/drm_dp_mst_topology.c
View file

@ -3414,7 +3414,7 @@ int drm_dp_add_payload_part2(struct drm_dp_mst_topology_mgr *mgr,
/* Skip failed payloads */
if (payload->vc_start_slot == -1) {
drm_dbg_kms(state->dev, "Part 1 of payload creation for %s failed, skipping part 2\n",
drm_dbg_kms(mgr->dev, "Part 1 of payload creation for %s failed, skipping part 2\n",
payload->port->connector->name);
return -EIO;
}

141
sys/dev/pci/drm/drm_bridge.c
View file

@ -698,6 +698,25 @@ void drm_atomic_bridge_chain_disable(struct drm_bridge *bridge,
}
EXPORT_SYMBOL(drm_atomic_bridge_chain_disable);
static void drm_atomic_bridge_call_post_disable(struct drm_bridge *bridge,
struct drm_atomic_state *old_state)
{
if (old_state && bridge->funcs->atomic_post_disable) {
struct drm_bridge_state *old_bridge_state;
old_bridge_state =
drm_atomic_get_old_bridge_state(old_state,
bridge);
if (WARN_ON(!old_bridge_state))
return;
bridge->funcs->atomic_post_disable(bridge,
old_bridge_state);
} else if (bridge->funcs->post_disable) {
bridge->funcs->post_disable(bridge);
}
}
/**
* drm_atomic_bridge_chain_post_disable - cleans up after disabling all bridges
* in the encoder chain
@ -709,36 +728,86 @@ EXPORT_SYMBOL(drm_atomic_bridge_chain_disable);
* starting from the first bridge to the last. These are called after completing
* &drm_encoder_helper_funcs.atomic_disable
*
* If a bridge sets @pre_enable_prev_first, then the @post_disable for that
* bridge will be called before the previous one to reverse the @pre_enable
* calling direction.
*
* Note: the bridge passed should be the one closest to the encoder
*/
void drm_atomic_bridge_chain_post_disable(struct drm_bridge *bridge,
struct drm_atomic_state *old_state)
{
struct drm_encoder *encoder;
struct drm_bridge *next, *limit;
if (!bridge)
return;
encoder = bridge->encoder;
list_for_each_entry_from(bridge, &encoder->bridge_chain, chain_node) {
if (bridge->funcs->atomic_post_disable) {
struct drm_bridge_state *old_bridge_state;
limit = NULL;
old_bridge_state =
drm_atomic_get_old_bridge_state(old_state,
bridge);
if (WARN_ON(!old_bridge_state))
return;
if (!list_is_last(&bridge->chain_node, &encoder->bridge_chain)) {
next = list_next_entry(bridge, chain_node);
bridge->funcs->atomic_post_disable(bridge,
old_bridge_state);
} else if (bridge->funcs->post_disable) {
bridge->funcs->post_disable(bridge);
if (next->pre_enable_prev_first) {
/* next bridge had requested that prev
* was enabled first, so disabled last
*/
limit = next;
/* Find the next bridge that has NOT requested
* prev to be enabled first / disabled last
*/
list_for_each_entry_from(next, &encoder->bridge_chain,
chain_node) {
if (next->pre_enable_prev_first) {
next = list_prev_entry(next, chain_node);
limit = next;
break;
}
}
/* Call these bridges in reverse order */
list_for_each_entry_from_reverse(next, &encoder->bridge_chain,
chain_node) {
if (next == bridge)
break;
drm_atomic_bridge_call_post_disable(next,
old_state);
}
}
}
drm_atomic_bridge_call_post_disable(bridge, old_state);
if (limit)
/* Jump all bridges that we have already post_disabled */
bridge = limit;
}
}
EXPORT_SYMBOL(drm_atomic_bridge_chain_post_disable);
static void drm_atomic_bridge_call_pre_enable(struct drm_bridge *bridge,
struct drm_atomic_state *old_state)
{
if (old_state && bridge->funcs->atomic_pre_enable) {
struct drm_bridge_state *old_bridge_state;
old_bridge_state =
drm_atomic_get_old_bridge_state(old_state,
bridge);
if (WARN_ON(!old_bridge_state))
return;
bridge->funcs->atomic_pre_enable(bridge, old_bridge_state);
} else if (bridge->funcs->pre_enable) {
bridge->funcs->pre_enable(bridge);
}
}
/**
* drm_atomic_bridge_chain_pre_enable - prepares for enabling all bridges in
* the encoder chain
@ -750,33 +819,61 @@ EXPORT_SYMBOL(drm_atomic_bridge_chain_post_disable);
* starting from the last bridge to the first. These are called before calling
* &drm_encoder_helper_funcs.atomic_enable
*
* If a bridge sets @pre_enable_prev_first, then the pre_enable for the
* prev bridge will be called before pre_enable of this bridge.
*
* Note: the bridge passed should be the one closest to the encoder
*/
void drm_atomic_bridge_chain_pre_enable(struct drm_bridge *bridge,
struct drm_atomic_state *old_state)
{
struct drm_encoder *encoder;
struct drm_bridge *iter;
struct drm_bridge *iter, *next, *limit;
if (!bridge)
return;
encoder = bridge->encoder;
list_for_each_entry_reverse(iter, &encoder->bridge_chain, chain_node) {
if (iter->funcs->atomic_pre_enable) {
struct drm_bridge_state *old_bridge_state;
if (iter->pre_enable_prev_first) {
next = iter;
limit = bridge;
list_for_each_entry_from_reverse(next,
&encoder->bridge_chain,
chain_node) {
if (next == bridge)
break;
old_bridge_state =
drm_atomic_get_old_bridge_state(old_state,
iter);
if (WARN_ON(!old_bridge_state))
return;
if (!next->pre_enable_prev_first) {
/* Found first bridge that does NOT
* request prev to be enabled first
*/
limit = list_prev_entry(next, chain_node);
break;
}
}
iter->funcs->atomic_pre_enable(iter, old_bridge_state);
} else if (iter->funcs->pre_enable) {
iter->funcs->pre_enable(iter);
list_for_each_entry_from(next, &encoder->bridge_chain, chain_node) {
/* Call requested prev bridge pre_enable
* in order.
*/
if (next == iter)
/* At the first bridge to request prev
* bridges called first.
*/
break;
drm_atomic_bridge_call_pre_enable(next, old_state);
}
}
drm_atomic_bridge_call_pre_enable(iter, old_state);
if (iter->pre_enable_prev_first)
/* Jump all bridges that we have already pre_enabled */
iter = limit;
if (iter == bridge)
break;
}

8
sys/dev/pci/drm/drm_gem.c
View file

@ -102,7 +102,7 @@ drm_fault(struct uvm_faultinfo *ufi, vaddr_t vaddr, vm_page_t *pps,
* we do not allow device mappings to be mapped copy-on-write
* so we kill any attempt to do so here.
*/
if (UVM_ET_ISCOPYONWRITE(entry)) {
uvmfault_unlockall(ufi, ufi->entry->aref.ar_amap, uobj);
return(VM_PAGER_ERROR);
@ -144,7 +144,7 @@ drm_fault(struct uvm_faultinfo *ufi, vaddr_t vaddr, vm_page_t *pps,
return (ret);
}
boolean_t
boolean_t
drm_flush(struct uvm_object *uobj, voff_t start, voff_t stop, int flags)
{
return (TRUE);
@ -309,10 +309,10 @@ int drm_gem_object_init(struct drm_device *dev,
printf("%s size too big %lu\n", __func__, size);
return -ENOMEM;
}
obj->uao = uao_create(size, 0);
uvm_obj_init(&obj->uobj, &drm_pgops, 1);
return 0;
}

131
sys/dev/pci/drm/drm_linux.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: drm_linux.c,v 1.99 2023/06/28 08:23:25 claudio Exp $ */
/* $OpenBSD: drm_linux.c,v 1.101 2023/07/18 06:58:59 claudio Exp $ */
/*
* Copyright (c) 2013 Jonathan Gray <jsg@openbsd.org>
* Copyright (c) 2015, 2016 Mark Kettenis <kettenis@openbsd.org>
@ -98,30 +98,30 @@ tasklet_run(void *arg)
struct mutex atomic64_mtx = MUTEX_INITIALIZER(IPL_HIGH);
#endif
struct mutex sch_mtx = MUTEX_INITIALIZER(IPL_SCHED);
volatile struct proc *sch_proc;
volatile void *sch_ident;
int sch_priority;
void
set_current_state(int state)
{
if (sch_ident != curproc)
mtx_enter(&sch_mtx);
MUTEX_ASSERT_LOCKED(&sch_mtx);
sch_ident = sch_proc = curproc;
sch_priority = state;
int prio = state;
KASSERT(state != TASK_RUNNING);
/* check if already on the sleep list */
if (curproc->p_wchan != NULL)
return;
sleep_setup(curproc, prio, "schto");
}
void
__set_current_state(int state)
{
struct proc *p = curproc;
int s;
KASSERT(state == TASK_RUNNING);
if (sch_ident == curproc) {
MUTEX_ASSERT_LOCKED(&sch_mtx);
sch_ident = NULL;
mtx_leave(&sch_mtx);
}
SCHED_LOCK(s);
unsleep(p);
p->p_stat = SONPROC;
atomic_clearbits_int(&p->p_flag, P_WSLEEP);
SCHED_UNLOCK(s);
}
void
@ -133,34 +133,19 @@ schedule(void)
long
schedule_timeout(long timeout)
{
struct sleep_state sls;
unsigned long deadline;
int wait, spl, prio, timo = 0;
int timo = 0;
MUTEX_ASSERT_LOCKED(&sch_mtx);
KASSERT(!cold);
if (timeout != MAX_SCHEDULE_TIMEOUT)
timo = timeout;
prio = sch_priority;
sleep_setup(&sls, sch_ident, prio, "schto");
wait = (sch_proc == curproc && timeout > 0);
spl = MUTEX_OLDIPL(&sch_mtx);
MUTEX_OLDIPL(&sch_mtx) = splsched();
mtx_leave(&sch_mtx);
if (timeout != MAX_SCHEDULE_TIMEOUT)
deadline = jiffies + timeout;
sleep_finish(&sls, prio, timo, wait);
sleep_finish(timo, timeout > 0);
if (timeout != MAX_SCHEDULE_TIMEOUT)
timeout = deadline - jiffies;
mtx_enter(&sch_mtx);
MUTEX_OLDIPL(&sch_mtx) = spl;
sch_ident = curproc;
return timeout > 0 ? timeout : 0;
}
@ -177,12 +162,43 @@ wake_up_process(struct proc *p)
int s, rv;
SCHED_LOCK(s);
atomic_cas_ptr(&sch_proc, p, NULL);
rv = wakeup_proc(p, NULL, 0);
SCHED_UNLOCK(s);
return rv;
}
int
autoremove_wake_function(struct wait_queue_entry *wqe, unsigned int mode,
int sync, void *key)
{
if (wqe->private)
wake_up_process(wqe->private);
list_del_init(&wqe->entry);
return 0;
}
void
prepare_to_wait(wait_queue_head_t *wqh, wait_queue_entry_t *wqe, int state)
{
mtx_enter(&wqh->lock);
if (list_empty(&wqe->entry))
__add_wait_queue(wqh, wqe);
mtx_leave(&wqh->lock);
set_current_state(state);
}
void
finish_wait(wait_queue_head_t *wqh, wait_queue_entry_t *wqe)
{
__set_current_state(TASK_RUNNING);
mtx_enter(&wqh->lock);
if (!list_empty(&wqe->entry))
list_del_init(&wqe->entry);
mtx_leave(&wqh->lock);
}
void
flush_workqueue(struct workqueue_struct *wq)
{
@ -257,7 +273,7 @@ kthread_run(int (*func)(void *), void *data, const char *name)
thread->func = func;
thread->data = data;
thread->flags = 0;
if (kthread_create(kthread_func, thread, &thread->proc, name)) {
free(thread, M_DRM, sizeof(*thread));
return ERR_PTR(-ENOMEM);
@ -278,7 +294,7 @@ kthread_create_worker(unsigned int flags, const char *fmt, ...)
vsnprintf(name, sizeof(name), fmt, ap);
va_end(ap);
w->tq = taskq_create(name, 1, IPL_HIGH, 0);
return w;
}
@ -287,7 +303,7 @@ kthread_destroy_worker(struct kthread_worker *worker)
{
taskq_destroy(worker->tq);
free(worker, M_DRM, sizeof(*worker));
}
void
@ -557,7 +573,7 @@ __free_pages(struct vm_page *page, unsigned int order)
{
struct pglist mlist;
int i;
TAILQ_INIT(&mlist);
for (i = 0; i < (1 << order); i++)
TAILQ_INSERT_TAIL(&mlist, &page[i], pageq);
@ -629,7 +645,7 @@ void
kunmap_atomic(void *addr)
{
KASSERT(kmap_atomic_inuse);
pmap_kremove(kmap_atomic_va, PAGE_SIZE);
kmap_atomic_inuse = 0;
}
@ -1199,7 +1215,7 @@ retry:
int
i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
{
int ret;
int ret;
if (adap->lock_ops)
adap->lock_ops->lock_bus(adap, 0);
@ -1503,7 +1519,7 @@ backlight_device_register(const char *name, void *kdev, void *data,
bd->data = data;
task_set(&bd->task, backlight_do_update_status, bd);
return bd;
}
@ -1726,7 +1742,7 @@ dma_fence_wait(struct dma_fence *fence, bool intr)
ret = dma_fence_wait_timeout(fence, intr, MAX_SCHEDULE_TIMEOUT);
if (ret < 0)
return ret;
return 0;
}
@ -1886,7 +1902,7 @@ dma_fence_default_wait(struct dma_fence *fence, bool intr, signed long timeout)
list_del(&cb.base.node);
out:
mtx_leave(fence->lock);
return ret;
}
@ -1932,7 +1948,7 @@ dma_fence_wait_any_timeout(struct dma_fence **fences, uint32_t count,
cb = mallocarray(count, sizeof(*cb), M_DRM, M_WAITOK|M_CANFAIL|M_ZERO);
if (cb == NULL)
return -ENOMEM;
for (i = 0; i < count; i++) {
struct dma_fence *fence = fences[i];
cb[i].proc = curproc;
@ -2028,7 +2044,7 @@ dma_fence_array_cb_func(struct dma_fence *f, struct dma_fence_cb *cb)
struct dma_fence_array_cb *array_cb =
container_of(cb, struct dma_fence_array_cb, cb);
struct dma_fence_array *dfa = array_cb->array;
if (atomic_dec_and_test(&dfa->num_pending))
timeout_add(&dfa->to, 1);
else
@ -2052,7 +2068,7 @@ dma_fence_array_enable_signaling(struct dma_fence *fence)
return false;
}
}
return true;
}
@ -2532,7 +2548,7 @@ pcie_get_speed_cap(struct pci_dev *pdev)
tag = pdev->tag;
if (!pci_get_capability(pc, tag, PCI_CAP_PCIEXPRESS,
&pos, NULL))
&pos, NULL))
return PCI_SPEED_UNKNOWN;
id = pci_conf_read(pc, tag, PCI_ID_REG);
@ -2588,7 +2604,7 @@ pcie_get_width_cap(struct pci_dev *pdev)
int bus, device, function;
if (!pci_get_capability(pc, tag, PCI_CAP_PCIEXPRESS,
&pos, NULL))
&pos, NULL))
return PCIE_LNK_WIDTH_UNKNOWN;
id = pci_conf_read(pc, tag, PCI_ID_REG);
@ -2613,25 +2629,14 @@ pcie_aspm_enabled(struct pci_dev *pdev)
pcireg_t lcsr;
if (!pci_get_capability(pc, tag, PCI_CAP_PCIEXPRESS,
&pos, NULL))
&pos, NULL))
return false;
lcsr = pci_conf_read(pc, tag, pos + PCI_PCIE_LCSR);
if ((lcsr & (PCI_PCIE_LCSR_ASPM_L0S | PCI_PCIE_LCSR_ASPM_L1)) != 0)
return true;
return false;
}
int
autoremove_wake_function(struct wait_queue_entry *wqe, unsigned int mode,
int sync, void *key)
{
wakeup(wqe);
if (wqe->private)
wake_up_process(wqe->private);
list_del_init(&wqe->entry);
return 0;
return false;
}
static wait_queue_head_t bit_waitq;
@ -2902,7 +2907,7 @@ interval_tree_iter_first(struct rb_root_cached *root, unsigned long start,
void
interval_tree_remove(struct interval_tree_node *node,
struct rb_root_cached *root)
struct rb_root_cached *root)
{
rb_erase_cached(&node->rb, root);
}
@ -3027,7 +3032,7 @@ fput(struct file *fp)
{
if (fp->f_type != DTYPE_SYNC)
return;
FRELE(fp, curproc);
}

2
sys/dev/pci/drm/drm_lock.c
View file

@ -223,7 +223,7 @@ int drm_legacy_lock(struct drm_device *dev, void *data,
ret ? "interrupted" : "has lock");
if (ret) return ret;
/* don't set the block all signals on the master process for now
/* don't set the block all signals on the master process for now
* really probably not the correct answer but lets us debug xkb
* xserver for now */
if (!drm_is_current_master(file_priv)) {

2
sys/dev/pci/drm/drm_managed.c
View file

@ -95,7 +95,7 @@ drmm_kfree(struct drm_device *dev, void *p)
}
}
mtx_leave(&dev->managed.lock);
if (m != NULL) {
free(m->p, M_DRM, m->size);
free(m, M_DRM, sizeof(*m));

2
sys/dev/pci/drm/drm_mm.c
View file

@ -174,7 +174,7 @@ drm_mm_interval_tree_iter_first(const struct rb_root_cached *root,
static void
drm_mm_interval_tree_remove(struct drm_mm_node *node,
struct rb_root_cached *root)
struct rb_root_cached *root)
{
rb_erase_cached(&node->rb, root);
}

8
sys/dev/pci/drm/i915/display/intel_ddi.c
View file

@ -3579,7 +3579,7 @@ static void intel_ddi_sync_state(struct intel_encoder *encoder,
enum phy phy = intel_port_to_phy(i915, encoder->port);
if (intel_phy_is_tc(i915, phy))
intel_tc_port_sanitize(enc_to_dig_port(encoder));
intel_tc_port_sanitize_mode(enc_to_dig_port(encoder));
if (crtc_state && intel_crtc_has_dp_encoder(crtc_state))
intel_dp_sync_state(encoder, crtc_state);
@ -3789,11 +3789,17 @@ static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
static void intel_ddi_encoder_reset(struct drm_encoder *encoder)
{
struct drm_i915_private *i915 = to_i915(encoder->dev);
struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
intel_dp->reset_link_params = true;
intel_pps_encoder_reset(intel_dp);
if (intel_phy_is_tc(i915, phy))
intel_tc_port_init_mode(dig_port);
}
static const struct drm_encoder_funcs intel_ddi_funcs = {

1
sys/dev/pci/drm/i915/display/intel_display_types.h
View file

@ -1763,6 +1763,7 @@ struct intel_digital_port {
bool tc_legacy_port:1;
char tc_port_name[8];
enum tc_port_mode tc_mode;
enum tc_port_mode tc_init_mode;
enum phy_fia tc_phy_fia;
u8 tc_phy_fia_idx;

4
sys/dev/pci/drm/i915/display/intel_psr.c
View file

@ -857,9 +857,9 @@ static bool _compute_psr2_wake_times(struct intel_dp *intel_dp,
}
io_wake_lines = intel_usecs_to_scanlines(
&crtc_state->uapi.adjusted_mode, io_wake_time);
&crtc_state->hw.adjusted_mode, io_wake_time);
fast_wake_lines = intel_usecs_to_scanlines(
&crtc_state->uapi.adjusted_mode, fast_wake_time);
&crtc_state->hw.adjusted_mode, fast_wake_time);
if (io_wake_lines > max_wake_lines ||
fast_wake_lines > max_wake_lines)

129
sys/dev/pci/drm/i915/display/intel_tc.c
View file

@ -5,6 +5,7 @@
#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_de.h"
#include "intel_display.h"
#include "intel_display_power_map.h"
#include "intel_display_types.h"
@ -116,6 +117,24 @@ assert_tc_cold_blocked(struct intel_digital_port *dig_port)
drm_WARN_ON(&i915->drm, !enabled);
}
static enum intel_display_power_domain
tc_port_power_domain(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
return POWER_DOMAIN_PORT_DDI_LANES_TC1 + tc_port - TC_PORT_1;
}
static void
assert_tc_port_power_enabled(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
drm_WARN_ON(&i915->drm,
!intel_display_power_is_enabled(i915, tc_port_power_domain(dig_port)));
}
u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
@ -683,22 +702,89 @@ static void intel_tc_port_update_mode(struct intel_digital_port *dig_port,
tc_cold_unblock(dig_port, domain, wref);
}
static void
intel_tc_port_link_init_refcount(struct intel_digital_port *dig_port,
int refcount)
static void __intel_tc_port_get_link(struct intel_digital_port *dig_port)
{
dig_port->tc_link_refcount++;
}
static void __intel_tc_port_put_link(struct intel_digital_port *dig_port)
{
dig_port->tc_link_refcount--;
}
static bool tc_port_is_enabled(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
drm_WARN_ON(&i915->drm, dig_port->tc_link_refcount);
dig_port->tc_link_refcount = refcount;
assert_tc_port_power_enabled(dig_port);
return intel_de_read(i915, DDI_BUF_CTL(dig_port->base.port)) &
DDI_BUF_CTL_ENABLE;
}
void intel_tc_port_sanitize(struct intel_digital_port *dig_port)
/**
* intel_tc_port_init_mode: Read out HW state and init the given port's TypeC mode
* @dig_port: digital port
*
* Read out the HW state and initialize the TypeC mode of @dig_port. The mode
* will be locked until intel_tc_port_sanitize_mode() is called.
*/
void intel_tc_port_init_mode(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
intel_wakeref_t tc_cold_wref;
enum intel_display_power_domain domain;
mutex_lock(&dig_port->tc_lock);
drm_WARN_ON(&i915->drm, dig_port->tc_mode != TC_PORT_DISCONNECTED);
drm_WARN_ON(&i915->drm, dig_port->tc_lock_wakeref);
drm_WARN_ON(&i915->drm, dig_port->tc_link_refcount);
tc_cold_wref = tc_cold_block(dig_port, &domain);
dig_port->tc_mode = intel_tc_port_get_current_mode(dig_port);
/*
* Save the initial mode for the state check in
* intel_tc_port_sanitize_mode().
*/
dig_port->tc_init_mode = dig_port->tc_mode;
dig_port->tc_lock_wakeref = tc_cold_block(dig_port, &dig_port->tc_lock_power_domain);
/*
* The PHY needs to be connected for AUX to work during HW readout and
* MST topology resume, but the PHY mode can only be changed if the
* port is disabled.
*/
if (!tc_port_is_enabled(dig_port))
intel_tc_port_update_mode(dig_port, 1, false);
/* Prevent changing dig_port->tc_mode until intel_tc_port_sanitize_mode() is called. */
__intel_tc_port_get_link(dig_port);
tc_cold_unblock(dig_port, domain, tc_cold_wref);
drm_dbg_kms(&i915->drm, "Port %s: init mode (%s)\n",
dig_port->tc_port_name,
tc_port_mode_name(dig_port->tc_mode));
mutex_unlock(&dig_port->tc_lock);
}
/**
* intel_tc_port_sanitize_mode: Sanitize the given port's TypeC mode
* @dig_port: digital port
*
* Sanitize @dig_port's TypeC mode wrt. the encoder's state right after driver
* loading and system resume:
* If the encoder is enabled keep the TypeC mode/PHY connected state locked until
* the encoder is disabled.
* If the encoder is disabled make sure the PHY is disconnected.
*/
void intel_tc_port_sanitize_mode(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
struct intel_encoder *encoder = &dig_port->base;
intel_wakeref_t tc_cold_wref;
enum intel_display_power_domain domain;
int active_links = 0;
mutex_lock(&dig_port->tc_lock);
@ -708,21 +794,12 @@ void intel_tc_port_sanitize(struct intel_digital_port *dig_port)
else if (encoder->base.crtc)
active_links = to_intel_crtc(encoder->base.crtc)->active;
drm_WARN_ON(&i915->drm, dig_port->tc_mode != TC_PORT_DISCONNECTED);
drm_WARN_ON(&i915->drm, dig_port->tc_lock_wakeref);
tc_cold_wref = tc_cold_block(dig_port, &domain);
dig_port->tc_mode = intel_tc_port_get_current_mode(dig_port);
drm_WARN_ON(&i915->drm, dig_port->tc_link_refcount != 1);
if (active_links) {
if (!icl_tc_phy_is_connected(dig_port))
drm_dbg_kms(&i915->drm,
"Port %s: PHY disconnected with %d active link(s)\n",
dig_port->tc_port_name, active_links);
intel_tc_port_link_init_refcount(dig_port, active_links);
dig_port->tc_lock_wakeref = tc_cold_block(dig_port,
&dig_port->tc_lock_power_domain);
} else {
/*
* TBT-alt is the default mode in any case the PHY ownership is not
@ -730,15 +807,17 @@ void intel_tc_port_sanitize(struct intel_digital_port *dig_port)
* we'll just switch to disconnected mode from it here without
* a note.
*/
if (dig_port->tc_mode != TC_PORT_TBT_ALT)
if (dig_port->tc_init_mode != TC_PORT_TBT_ALT)
drm_dbg_kms(&i915->drm,
"Port %s: PHY left in %s mode on disabled port, disconnecting it\n",
dig_port->tc_port_name,
tc_port_mode_name(dig_port->tc_mode));
tc_port_mode_name(dig_port->tc_init_mode));
icl_tc_phy_disconnect(dig_port);
}
__intel_tc_port_put_link(dig_port);
tc_cold_unblock(dig_port, domain, tc_cold_wref);
tc_cold_unblock(dig_port, dig_port->tc_lock_power_domain,
fetch_and_zero(&dig_port->tc_lock_wakeref));
}
drm_dbg_kms(&i915->drm, "Port %s: sanitize mode (%s)\n",
dig_port->tc_port_name,
@ -846,14 +925,14 @@ void intel_tc_port_get_link(struct intel_digital_port *dig_port,
int required_lanes)
{
__intel_tc_port_lock(dig_port, required_lanes);
dig_port->tc_link_refcount++;
__intel_tc_port_get_link(dig_port);
intel_tc_port_unlock(dig_port);
}
void intel_tc_port_put_link(struct intel_digital_port *dig_port)
{
intel_tc_port_lock(dig_port);
--dig_port->tc_link_refcount;
__intel_tc_port_put_link(dig_port);
intel_tc_port_unlock(dig_port);
/*
@ -923,4 +1002,6 @@ void intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy)
dig_port->tc_mode = TC_PORT_DISCONNECTED;
dig_port->tc_link_refcount = 0;
tc_port_load_fia_params(i915, dig_port);
intel_tc_port_init_mode(dig_port);
}

3
sys/dev/pci/drm/i915/display/intel_tc.h
View file

@ -24,7 +24,8 @@ int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port);
void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
int required_lanes);
void intel_tc_port_sanitize(struct intel_digital_port *dig_port);
void intel_tc_port_init_mode(struct intel_digital_port *dig_port);
void intel_tc_port_sanitize_mode(struct intel_digital_port *dig_port);
void intel_tc_port_lock(struct intel_digital_port *dig_port);
void intel_tc_port_unlock(struct intel_digital_port *dig_port);
void intel_tc_port_flush_work(struct intel_digital_port *dig_port);

2
sys/dev/pci/drm/i915/gt/agp_intel_gtt.c
View file

@ -177,7 +177,7 @@ intel_gmch_gtt_get(u64 *gtt_total,
{
struct inteldrm_softc *dev_priv = (void *)inteldrm_cd.cd_devs[0];
struct agp_info *ai = &dev_priv->drm.agp->info;
*gtt_total = ai->ai_aperture_size;
*mappable_base = ai->ai_aperture_base;
*mappable_end = ai->ai_aperture_size;

2
sys/dev/pci/drm/i915/gt/shmem_utils.c
View file

@ -228,7 +228,7 @@ static int __uao_rw(struct uvm_object *uao, loff_t off,
unsigned int this =
min_t(size_t, PAGE_SIZE - offset_in_page(off), len);
void *vaddr = kmap(page);
if (write) {
memcpy(vaddr + offset_in_page(off), ptr, this);
set_page_dirty(page);

2
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
View file

@ -580,7 +580,7 @@ static int slpc_set_softlimits(struct intel_guc_slpc *slpc)
if (unlikely(ret))
return ret;
slpc_to_gt(slpc)->defaults.min_freq = slpc->min_freq_softlimit;
} else if (slpc->min_freq_softlimit != slpc->min_freq) {
} else {
return intel_guc_slpc_set_min_freq(slpc,
slpc->min_freq_softlimit);
}

8
sys/dev/pci/drm/include/drm/drm_bridge.h
View file

@ -768,6 +768,14 @@ struct drm_bridge {
* modes.
*/
bool interlace_allowed;
/**
* @pre_enable_prev_first: The bridge requires that the prev
* bridge @pre_enable function is called before its @pre_enable,
* and conversely for post_disable. This is most frequently a
* requirement for DSI devices which need the host to be initialised
* before the peripheral.
*/
bool pre_enable_prev_first;
/**
* @ddc: Associated I2C adapter for DDC access, if any.
*/

6
sys/dev/pci/drm/include/drm/drm_fixed.h
View file

@ -70,6 +70,7 @@ static inline u32 dfixed_div(fixed20_12 A, fixed20_12 B)
}
#define DRM_FIXED_POINT 32
#define DRM_FIXED_POINT_HALF 16
#define DRM_FIXED_ONE (1ULL << DRM_FIXED_POINT)
#define DRM_FIXED_DECIMAL_MASK (DRM_FIXED_ONE - 1)
#define DRM_FIXED_DIGITS_MASK (~DRM_FIXED_DECIMAL_MASK)
@ -86,6 +87,11 @@ static inline int drm_fixp2int(s64 a)
return ((s64)a) >> DRM_FIXED_POINT;
}
static inline int drm_fixp2int_round(s64 a)
{
return drm_fixp2int(a + (1 << (DRM_FIXED_POINT_HALF - 1)));
}
static inline int drm_fixp2int_ceil(s64 a)
{
if (a > 0)

6
sys/dev/pci/drm/include/linux/atomic.h
View file

@ -2,7 +2,7 @@
/**
* \file drm_atomic.h
* Atomic operations used in the DRM which may or may not be provided by the OS.
*
*
* \author Eric Anholt <anholt@FreeBSD.org>
*/
@ -298,7 +298,7 @@ __test_and_set_bit(u_int b, volatile void *p)
volatile u_int *ptr = (volatile u_int *)p;
unsigned int prev = ptr[b >> 5];
ptr[b >> 5] |= m;
return (prev & m) != 0;
}
@ -428,7 +428,7 @@ find_next_bit(const volatile void *p, int max, int b)
#define wmb() __membar("dsb sy")
#define mb() __membar("dsb sy")
#elif defined(__mips64__)
#define rmb() mips_sync()
#define rmb() mips_sync()
#define wmb() mips_sync()
#define mb() mips_sync()
#elif defined(__powerpc64__)

6
sys/dev/pci/drm/include/linux/capability.h
View file

@ -12,8 +12,8 @@
#define CAP_SYS_NICE 0x2
static inline bool
capable(int cap)
{
capable(int cap)
{
switch (cap) {
case CAP_SYS_ADMIN:
case CAP_SYS_NICE:
@ -21,7 +21,7 @@ capable(int cap)
default:
panic("unhandled capability");
}
}
}
static inline bool
perfmon_capable(void)

2
sys/dev/pci/drm/include/linux/dma-buf.h
View file

@ -61,7 +61,7 @@ struct dma_buf_export_info {
struct dma_resv *resv;
};
#define DEFINE_DMA_BUF_EXPORT_INFO(x) struct dma_buf_export_info x
#define DEFINE_DMA_BUF_EXPORT_INFO(x) struct dma_buf_export_info x
struct dma_buf *dma_buf_export(const struct dma_buf_export_info *);

2
sys/dev/pci/drm/include/linux/file.h
View file

@ -4,7 +4,7 @@
#define _LINUX_FILE_H
/* both for printf */
#include <sys/types.h>
#include <sys/types.h>
#include <sys/systm.h>
void fd_install(int, struct file *);

2
sys/dev/pci/drm/include/linux/interrupt.h
View file

@ -106,7 +106,7 @@ tasklet_hi_schedule(struct tasklet_struct *ts)
task_add(taskletq, &ts->task);
}
static inline void
static inline void
tasklet_disable_nosync(struct tasklet_struct *ts)
{
atomic_inc(&ts->count);

2
sys/dev/pci/drm/include/linux/io.h
View file

@ -119,7 +119,7 @@ static inline u32
ioread32(const volatile void __iomem *addr)
{
uint32_t val;
iobarrier();
val = lemtoh32(addr);
rmb();

12
sys/dev/pci/drm/include/linux/pci.h
View file

@ -135,7 +135,7 @@ pci_read_config_dword(struct pci_dev *pdev, int reg, u32 *val)
{
*val = pci_conf_read(pdev->pc, pdev->tag, reg);
return 0;
}
}
static inline int
pci_read_config_word(struct pci_dev *pdev, int reg, u16 *val)
@ -145,7 +145,7 @@ pci_read_config_word(struct pci_dev *pdev, int reg, u16 *val)
v = pci_conf_read(pdev->pc, pdev->tag, (reg & ~0x2));
*val = (v >> ((reg & 0x2) * 8));
return 0;
}
}
static inline int
pci_read_config_byte(struct pci_dev *pdev, int reg, u8 *val)
@ -155,14 +155,14 @@ pci_read_config_byte(struct pci_dev *pdev, int reg, u8 *val)
v = pci_conf_read(pdev->pc, pdev->tag, (reg & ~0x3));
*val = (v >> ((reg & 0x3) * 8));
return 0;
}
}
static inline int
pci_write_config_dword(struct pci_dev *pdev, int reg, u32 val)
{
pci_conf_write(pdev->pc, pdev->tag, reg, val);
return 0;
}
}
static inline int
pci_write_config_word(struct pci_dev *pdev, int reg, u16 val)
@ -174,7 +174,7 @@ pci_write_config_word(struct pci_dev *pdev, int reg, u16 val)
v |= (val << ((reg & 0x2) * 8));
pci_conf_write(pdev->pc, pdev->tag, (reg & ~0x2), v);
return 0;
}
}
static inline int
pci_write_config_byte(struct pci_dev *pdev, int reg, u8 val)
@ -319,7 +319,7 @@ static inline int
pcie_set_readrq(struct pci_dev *pdev, int rrq)
{
uint16_t val;
pcie_capability_read_word(pdev, PCI_PCIE_DCSR, &val);
val &= ~PCI_PCIE_DCSR_MPS;
val |= (ffs(rrq) - 8) << 12;

2
sys/dev/pci/drm/include/linux/rbtree.h
View file

@ -99,7 +99,7 @@ __rb_deepest_left(struct rb_node *node)
else
node = RB_RIGHT(node, __entry);
}
return parent;
return parent;
}
static inline struct rb_node *

2
sys/dev/pci/drm/include/linux/scatterlist.h
View file

@ -77,7 +77,7 @@ static inline bool
__sg_page_iter_next(struct sg_page_iter *iter)
{
iter->sg_pgoffset++;
while (iter->__nents > 0 &&
while (iter->__nents > 0 &&
iter->sg_pgoffset >= (iter->sg->length / PAGE_SIZE)) {
iter->sg_pgoffset -= (iter->sg->length / PAGE_SIZE);
iter->sg++;

2
sys/dev/pci/drm/include/linux/seqlock.h
View file

@ -91,7 +91,7 @@ typedef struct {
static inline void
seqlock_init(seqlock_t *sl, int wantipl)
{
{
sl->seq = 0;
mtx_init(&sl->lock, wantipl);
}

2
sys/dev/pci/drm/include/linux/string.h
View file

@ -74,7 +74,7 @@ match_string(const char * const *array, size_t n, const char *str)
for (i = 0; i < n; i++) {
if (array[i] == NULL)
break;
if (!strcmp(array[i], str))
if (!strcmp(array[i], str))
return i;
}

4
sys/dev/pci/drm/include/linux/swap.h
View file

@ -30,11 +30,11 @@
static inline long
get_nr_swap_pages(void)
{
{
return uvmexp.swpages - uvmexp.swpginuse;
}
/*
/*
* XXX For now, we don't want the shrinker to be too aggressive, so
* pretend we're not called from the pagedaemon even if we are.
*/

88
sys/dev/pci/drm/include/linux/wait.h
View file

@ -1,4 +1,4 @@
/* $OpenBSD: wait.h,v 1.9 2023/01/01 01:34:58 jsg Exp $ */
/* $OpenBSD: wait.h,v 1.10 2023/07/18 06:58:59 claudio Exp $ */
/*
* Copyright (c) 2013, 2014, 2015 Mark Kettenis
* Copyright (c) 2017 Martin Pieuchot
@ -22,6 +22,7 @@
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/mutex.h>
#include <sys/proc.h>
#include <linux/list.h>
#include <linux/errno.h>
@ -36,17 +37,15 @@ struct wait_queue_entry {
typedef struct wait_queue_entry wait_queue_entry_t;
extern struct mutex sch_mtx;
extern volatile struct proc *sch_proc;
extern volatile void *sch_ident;
extern int sch_priority;
struct wait_queue_head {
struct mutex lock;
struct list_head head;
};
typedef struct wait_queue_head wait_queue_head_t;
void prepare_to_wait(wait_queue_head_t *, wait_queue_entry_t *, int);
void finish_wait(wait_queue_head_t *, wait_queue_entry_t *);
static inline void
init_waitqueue_head(wait_queue_head_t *wqh)
{
@ -103,30 +102,36 @@ remove_wait_queue(wait_queue_head_t *head, wait_queue_entry_t *old)
#define __wait_event_intr_timeout(wqh, condition, timo, prio) \
({ \
long ret = timo; \
long __ret = timo; \
struct wait_queue_entry __wq_entry; \
\
init_wait_entry(&__wq_entry, 0); \
do { \
int __error; \
int __error, __wait; \
unsigned long deadline; \
\
KASSERT(!cold); \
\
mtx_enter(&sch_mtx); \
deadline = jiffies + ret; \
__error = msleep(&wqh, &sch_mtx, prio, "drmweti", ret); \
ret = deadline - jiffies; \
prepare_to_wait(&wqh, &__wq_entry, prio); \
deadline = jiffies + __ret; \
\
__wait = !(condition); \
\
__error = sleep_finish(__ret, __wait); \
if ((timo) > 0) \
__ret = deadline - jiffies; \
\
if (__error == ERESTART || __error == EINTR) { \
ret = -ERESTARTSYS; \
mtx_leave(&sch_mtx); \
__ret = -ERESTARTSYS; \
break; \
} \
if ((timo) > 0 && (ret <= 0 || __error == EWOULDBLOCK)) { \
mtx_leave(&sch_mtx); \
ret = ((condition)) ? 1 : 0; \
if ((timo) > 0 && (__ret <= 0 || __error == EWOULDBLOCK)) { \
__ret = ((condition)) ? 1 : 0; \
break; \
} \
mtx_leave(&sch_mtx); \
} while (ret > 0 && !(condition)); \
ret; \
} while (__ret > 0 && !(condition)); \
finish_wait(&wqh, &__wq_entry); \
__ret; \
})
/*
@ -194,15 +199,23 @@ do { \
#define __wait_event_lock_irq(wqh, condition, mtx) \
({ \
struct wait_queue_entry __wq_entry; \
\
init_wait_entry(&__wq_entry, 0); \
do { \
int __wait; \
\
KASSERT(!cold); \
\
prepare_to_wait(&wqh, &__wq_entry, 0); \
\
__wait = !(condition); \
\
mtx_leave(&(mtx)); \
mtx_enter(&sch_mtx); \
msleep(&wqh, &sch_mtx, 0, "drmweli", 0); \
mtx_leave(&sch_mtx); \
sleep_finish(0, __wait); \
mtx_enter(&(mtx)); \
} while (!(condition)); \
finish_wait(&wqh, &__wq_entry); \
})
/*
@ -221,13 +234,12 @@ wake_up(wait_queue_head_t *wqh)
wait_queue_entry_t *wqe;
wait_queue_entry_t *tmp;
mtx_enter(&wqh->lock);
list_for_each_entry_safe(wqe, tmp, &wqh->head, entry) {
KASSERT(wqe->func != NULL);
if (wqe->func != NULL)
wqe->func(wqe, 0, wqe->flags, NULL);
}
wakeup(wqh);
mtx_leave(&wqh->lock);
}
@ -244,7 +256,6 @@ wake_up_all_locked(wait_queue_head_t *wqh)
if (wqe->func != NULL)
wqe->func(wqe, 0, wqe->flags, NULL);
}
wakeup(wqh);
}
#define wake_up_interruptible(wqh) wake_up(wqh)
@ -255,31 +266,6 @@ wake_up_all_locked(wait_queue_head_t *wqh)
.private = curproc, \
.func = autoremove_wake_function, \
.entry = LIST_HEAD_INIT((name).entry), \
}
static inline void
prepare_to_wait(wait_queue_head_t *wqh, wait_queue_entry_t *wqe, int state)
{
if (wqe->flags == 0) {
mtx_enter(&sch_mtx);
wqe->flags = 1;
}
MUTEX_ASSERT_LOCKED(&sch_mtx);
if (list_empty(&wqe->entry))
__add_wait_queue(wqh, wqe);
sch_proc = curproc;
sch_ident = wqe;
sch_priority = state;
}
static inline void
finish_wait(wait_queue_head_t *wqh, wait_queue_entry_t *wqe)
{
MUTEX_ASSERT_LOCKED(&sch_mtx);
sch_ident = NULL;
if (!list_empty(&wqe->entry))
list_del_init(&wqe->entry);
mtx_leave(&sch_mtx);
}
#endif

4
sys/dev/pci/drm/include/linux/ww_mutex.h
View file

@ -209,7 +209,7 @@ static inline int
ww_mutex_lock(struct ww_mutex *lock, struct ww_acquire_ctx *ctx) {
return __ww_mutex_lock(lock, ctx, false, false);
}
static inline void
ww_mutex_lock_slow(struct ww_mutex *lock, struct ww_acquire_ctx *ctx) {
(void)__ww_mutex_lock(lock, ctx, true, false);
@ -219,7 +219,7 @@ static inline int
ww_mutex_lock_interruptible(struct ww_mutex *lock, struct ww_acquire_ctx *ctx) {
return __ww_mutex_lock(lock, ctx, false, true);
}
static inline int __must_check
ww_mutex_lock_slow_interruptible(struct ww_mutex *lock, struct ww_acquire_ctx *ctx) {
return __ww_mutex_lock(lock, ctx, true, true);

2
sys/dev/pci/drm/include/uapi/drm/radeon_drm.h
View file

@ -233,7 +233,7 @@ typedef union {
# define R300_WAIT_3D 0x2
/* these two defines are DOING IT WRONG - however
* we have userspace which relies on using these.
* The wait interface is backwards compat new
* The wait interface is backwards compat new
* code should use the NEW_WAIT defines below
* THESE ARE NOT BIT FIELDS
*/

4
sys/dev/pci/drm/linux_sort.c
View file

@ -56,7 +56,7 @@ static __inline void swapfunc(char *, char *, size_t, int);
static __inline void
swapfunc(char *a, char *b, size_t n, int swaptype)
{
if (swaptype <= 1)
if (swaptype <= 1)
swapcode(long, a, b, n)
else
swapcode(char, a, b, n)
@ -167,7 +167,7 @@ loop: SWAPINIT(a, es);
void
sort(void *a, size_t n, size_t es, int (*cmp)(const void *, const void *),
void *x)
void *x)
{
KASSERT(x == NULL);
qsort(a, n, es, cmp);

24
sys/dev/pci/drm/radeon/ObjectID.h
View file

@ -1,5 +1,5 @@
/*
* Copyright 2006-2007 Advanced Micro Devices, Inc.
* Copyright 2006-2007 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -37,13 +37,13 @@
#define GRAPH_OBJECT_TYPE_CONNECTOR 0x3
#define GRAPH_OBJECT_TYPE_ROUTER 0x4
/* deleted */
#define GRAPH_OBJECT_TYPE_DISPLAY_PATH 0x6
#define GRAPH_OBJECT_TYPE_DISPLAY_PATH 0x6
#define GRAPH_OBJECT_TYPE_GENERIC 0x7
/****************************************************/
/* Encoder Object ID Definition */
/****************************************************/
#define ENCODER_OBJECT_ID_NONE 0x00
#define ENCODER_OBJECT_ID_NONE 0x00
/* Radeon Class Display Hardware */
#define ENCODER_OBJECT_ID_INTERNAL_LVDS 0x01
@ -96,7 +96,7 @@
/****************************************************/
/* Connector Object ID Definition */
/****************************************************/
#define CONNECTOR_OBJECT_ID_NONE 0x00
#define CONNECTOR_OBJECT_ID_NONE 0x00
#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I 0x01
#define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I 0x02
#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D 0x03
@ -156,7 +156,7 @@
#define RESERVED1_ID_MASK 0x0800
#define OBJECT_TYPE_MASK 0x7000
#define RESERVED2_ID_MASK 0x8000
#define OBJECT_ID_SHIFT 0x00
#define ENUM_ID_SHIFT 0x08
#define OBJECT_TYPE_SHIFT 0x0C
@ -177,14 +177,14 @@
/* Encoder Object ID definition - Shared with BIOS */
/****************************************************/
/*
#define ENCODER_INTERNAL_LVDS_ENUM_ID1 0x2101
#define ENCODER_INTERNAL_LVDS_ENUM_ID1 0x2101
#define ENCODER_INTERNAL_TMDS1_ENUM_ID1 0x2102
#define ENCODER_INTERNAL_TMDS2_ENUM_ID1 0x2103
#define ENCODER_INTERNAL_DAC1_ENUM_ID1 0x2104
#define ENCODER_INTERNAL_DAC2_ENUM_ID1 0x2105
#define ENCODER_INTERNAL_SDVOA_ENUM_ID1 0x2106
#define ENCODER_INTERNAL_SDVOB_ENUM_ID1 0x2107
#define ENCODER_SIL170B_ENUM_ID1 0x2108
#define ENCODER_SIL170B_ENUM_ID1 0x2108
#define ENCODER_CH7303_ENUM_ID1 0x2109
#define ENCODER_CH7301_ENUM_ID1 0x210A
#define ENCODER_INTERNAL_DVO1_ENUM_ID1 0x210B
@ -198,8 +198,8 @@
#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 0x2113
#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 0x2114
#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 0x2115
#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 0x2116
#define ENCODER_SI178_ENUM_ID1 0x2117
#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 0x2116
#define ENCODER_SI178_ENUM_ID1 0x2117
#define ENCODER_MVPU_FPGA_ENUM_ID1 0x2118
#define ENCODER_INTERNAL_DDI_ENUM_ID1 0x2119
#define ENCODER_VT1625_ENUM_ID1 0x211A
@ -314,7 +314,7 @@
#define ENCODER_SI178_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT)
ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT)
#define ENCODER_MVPU_FPGA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
@ -322,7 +322,7 @@
#define ENCODER_INTERNAL_DDI_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT)
ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT)
#define ENCODER_VT1625_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
@ -350,7 +350,7 @@
#define ENCODER_INTERNAL_KLDSCP_LVTMA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT)
ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT)
#define ENCODER_INTERNAL_UNIPHY1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\

1780
sys/dev/pci/drm/radeon/atombios.h
View file

File diff suppressed because it is too large Load diff

28
sys/dev/pci/drm/radeon/ci_dpm.c
View file

@ -5517,6 +5517,7 @@ static int ci_parse_power_table(struct radeon_device *rdev)
u8 frev, crev;
u8 *power_state_offset;
struct ci_ps *ps;
int ret;
if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
&frev, &crev, &data_offset))
@ -5546,11 +5547,15 @@ static int ci_parse_power_table(struct radeon_device *rdev)
non_clock_array_index = power_state->v2.nonClockInfoIndex;
non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
&non_clock_info_array->nonClockInfo[non_clock_array_index];
if (!rdev->pm.power_state[i].clock_info)
return -EINVAL;
if (!rdev->pm.power_state[i].clock_info) {
ret = -EINVAL;
goto err_free_ps;
}
ps = kzalloc(sizeof(struct ci_ps), GFP_KERNEL);
if (ps == NULL)
return -ENOMEM;
if (ps == NULL) {
ret = -ENOMEM;
goto err_free_ps;
}
rdev->pm.dpm.ps[i].ps_priv = ps;
ci_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
non_clock_info,
@ -5590,6 +5595,12 @@ static int ci_parse_power_table(struct radeon_device *rdev)
}
return 0;
err_free_ps:
for (i = 0; i < rdev->pm.dpm.num_ps; i++)
kfree(rdev->pm.dpm.ps[i].ps_priv);
kfree(rdev->pm.dpm.ps);
return ret;
}
static int ci_get_vbios_boot_values(struct radeon_device *rdev,
@ -5678,25 +5689,26 @@ int ci_dpm_init(struct radeon_device *rdev)
ret = ci_get_vbios_boot_values(rdev, &pi->vbios_boot_state);
if (ret) {
ci_dpm_fini(rdev);
kfree(rdev->pm.dpm.priv);
return ret;
}
ret = r600_get_platform_caps(rdev);
if (ret) {
ci_dpm_fini(rdev);
kfree(rdev->pm.dpm.priv);
return ret;
}
ret = r600_parse_extended_power_table(rdev);
if (ret) {
ci_dpm_fini(rdev);
kfree(rdev->pm.dpm.priv);
return ret;
}
ret = ci_parse_power_table(rdev);
if (ret) {
ci_dpm_fini(rdev);
kfree(rdev->pm.dpm.priv);
r600_free_extended_power_table(rdev);
return ret;
}

8
sys/dev/pci/drm/radeon/cypress_dpm.c
View file

@ -557,8 +557,12 @@ static int cypress_populate_mclk_value(struct radeon_device *rdev,
ASIC_INTERNAL_MEMORY_SS, vco_freq)) {
u32 reference_clock = rdev->clock.mpll.reference_freq;
u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div);
u32 clk_s = reference_clock * 5 / (decoded_ref * ss.rate);
u32 clk_v = ss.percentage *
u32 clk_s, clk_v;
if (!decoded_ref)
return -EINVAL;
clk_s = reference_clock * 5 / (decoded_ref * ss.rate);
clk_v = ss.percentage *
(0x4000 * dividers.whole_fb_div + 0x800 * dividers.frac_fb_div) / (clk_s * 625);
mpll_ss1 &= ~CLKV_MASK;

2
sys/dev/pci/drm/radeon/evergreen.c
View file

@ -2941,7 +2941,7 @@ void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
if (ring->rptr_save_reg) {
next_rptr = ring->wptr + 3 + 4;
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
radeon_ring_write(ring, ((ring->rptr_save_reg -
radeon_ring_write(ring, ((ring->rptr_save_reg -
PACKET3_SET_CONFIG_REG_START) >> 2));
radeon_ring_write(ring, next_rptr);
} else if (rdev->wb.enabled) {

2
sys/dev/pci/drm/radeon/ni.c
View file

@ -1423,7 +1423,7 @@ void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
if (ring->rptr_save_reg) {
uint32_t next_rptr = ring->wptr + 3 + 4 + 8;
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
radeon_ring_write(ring, ((ring->rptr_save_reg -
radeon_ring_write(ring, ((ring->rptr_save_reg -
PACKET3_SET_CONFIG_REG_START) >> 2));
radeon_ring_write(ring, next_rptr);
}

8
sys/dev/pci/drm/radeon/ni_dpm.c
View file

@ -2241,8 +2241,12 @@ static int ni_populate_mclk_value(struct radeon_device *rdev,
ASIC_INTERNAL_MEMORY_SS, vco_freq)) {
u32 reference_clock = rdev->clock.mpll.reference_freq;
u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div);
u32 clk_s = reference_clock * 5 / (decoded_ref * ss.rate);
u32 clk_v = ss.percentage *
u32 clk_s, clk_v;
if (!decoded_ref)
return -EINVAL;
clk_s = reference_clock * 5 / (decoded_ref * ss.rate);
clk_v = ss.percentage *
(0x4000 * dividers.whole_fb_div + 0x800 * dividers.frac_fb_div) / (clk_s * 625);
mpll_ss1 &= ~CLKV_MASK;

46
sys/dev/pci/drm/radeon/pptable.h
View file

@ -114,8 +114,8 @@ typedef struct _ATOM_PPLIB_EXTENDEDHEADER
USHORT usUVDTableOffset; //points to ATOM_PPLIB_UVD_Table
USHORT usSAMUTableOffset; //points to ATOM_PPLIB_SAMU_Table
USHORT usPPMTableOffset; //points to ATOM_PPLIB_PPM_Table
USHORT usACPTableOffset; //points to ATOM_PPLIB_ACP_Table
USHORT usPowerTuneTableOffset; //points to ATOM_PPLIB_POWERTUNE_Table
USHORT usACPTableOffset; //points to ATOM_PPLIB_ACP_Table
USHORT usPowerTuneTableOffset; //points to ATOM_PPLIB_POWERTUNE_Table
} ATOM_PPLIB_EXTENDEDHEADER;
//// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps
@ -196,14 +196,14 @@ typedef struct _ATOM_PPLIB_POWERPLAYTABLE3
typedef struct _ATOM_PPLIB_POWERPLAYTABLE4
{
ATOM_PPLIB_POWERPLAYTABLE3 basicTable3;
ULONG ulGoldenPPID; // PPGen use only
ULONG ulGoldenPPID; // PPGen use only
ULONG ulGoldenRevision; // PPGen use only
USHORT usVddcDependencyOnSCLKOffset;
USHORT usVddciDependencyOnMCLKOffset;
USHORT usVddcDependencyOnMCLKOffset;
USHORT usMaxClockVoltageOnDCOffset;
USHORT usVddcPhaseShedLimitsTableOffset; // Points to ATOM_PPLIB_PhaseSheddingLimits_Table
USHORT usMvddDependencyOnMCLKOffset;
USHORT usMvddDependencyOnMCLKOffset;
} ATOM_PPLIB_POWERPLAYTABLE4, *LPATOM_PPLIB_POWERPLAYTABLE4;
typedef struct _ATOM_PPLIB_POWERPLAYTABLE5
@ -347,23 +347,23 @@ typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO
UCHAR ucPadding; // For proper alignment and size.
USHORT usVDDC; // For the 780, use: None, Low, High, Variable
UCHAR ucMaxHTLinkWidth; // From SBIOS - {2, 4, 8, 16}
UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could
UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could
USHORT usHTLinkFreq; // See definition ATOM_PPLIB_RS780_HTLINKFREQ_xxx or in MHz(>=200).
ULONG ulFlags;
ULONG ulFlags;
} ATOM_PPLIB_RS780_CLOCK_INFO;
#define ATOM_PPLIB_RS780_VOLTAGE_NONE 0
#define ATOM_PPLIB_RS780_VOLTAGE_LOW 1
#define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2
#define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3
#define ATOM_PPLIB_RS780_VOLTAGE_NONE 0
#define ATOM_PPLIB_RS780_VOLTAGE_LOW 1
#define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2
#define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3
#define ATOM_PPLIB_RS780_SPMCLK_NONE 0 // We cannot change the side port memory clock, leave it as it is.
#define ATOM_PPLIB_RS780_SPMCLK_LOW 1
#define ATOM_PPLIB_RS780_SPMCLK_HIGH 2
#define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0
#define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1
#define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2
#define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0
#define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1
#define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2
typedef struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO
{
@ -405,14 +405,14 @@ typedef struct _ATOM_PPLIB_CI_CLOCK_INFO
USHORT usMemoryClockLow;
UCHAR ucMemoryClockHigh;
UCHAR ucPCIEGen;
USHORT usPCIELane;
} ATOM_PPLIB_CI_CLOCK_INFO;
typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO{
USHORT usEngineClockLow; //clockfrequency & 0xFFFF. The unit is in 10khz
UCHAR ucEngineClockHigh; //clockfrequency >> 16.
UCHAR ucEngineClockHigh; //clockfrequency >> 16.
UCHAR vddcIndex; //2-bit vddc index;
USHORT tdpLimit;
//please initalize to 0
@ -423,10 +423,10 @@ typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO{
typedef struct _ATOM_PPLIB_STATE_V2
{
//number of valid dpm levels in this state; Driver uses it to calculate the whole
//number of valid dpm levels in this state; Driver uses it to calculate the whole
//size of the state: sizeof(ATOM_PPLIB_STATE_V2) + (ucNumDPMLevels - 1) * sizeof(UCHAR)
UCHAR ucNumDPMLevels;
//a index to the array of nonClockInfos
UCHAR nonClockInfoIndex;
/**
@ -436,9 +436,9 @@ typedef struct _ATOM_PPLIB_STATE_V2
} ATOM_PPLIB_STATE_V2;
typedef struct _StateArray{
//how many states we have
//how many states we have
UCHAR ucNumEntries;
ATOM_PPLIB_STATE_V2 states[1];
}StateArray;
@ -446,10 +446,10 @@ typedef struct _StateArray{
typedef struct _ClockInfoArray{
//how many clock levels we have
UCHAR ucNumEntries;
//sizeof(ATOM_PPLIB_CLOCK_INFO)
UCHAR ucEntrySize;
UCHAR clockInfo[1];
}ClockInfoArray;
@ -459,7 +459,7 @@ typedef struct _NonClockInfoArray{
UCHAR ucNumEntries;
//sizeof(ATOM_PPLIB_NONCLOCK_INFO)
UCHAR ucEntrySize;
ATOM_PPLIB_NONCLOCK_INFO nonClockInfo[1];
}NonClockInfoArray;
@ -680,7 +680,7 @@ typedef struct _ATOM_PPLIB_PPM_Table
ULONG ulPlatformTDC;
ULONG ulSmallACPlatformTDC;
ULONG ulApuTDP;
ULONG ulDGpuTDP;
ULONG ulDGpuTDP;
ULONG ulDGpuUlvPower;
ULONG ulTjmax;
} ATOM_PPLIB_PPM_Table;

10
sys/dev/pci/drm/radeon/radeon_bios.c
View file

@ -92,7 +92,7 @@ static bool igp_read_bios_from_vram(struct radeon_device *rdev)
bus_size_t size = 256 * 1024; /* ??? */
bus_space_handle_t bsh;
bus_space_tag_t bst = rdev->memt;
if (!(rdev->flags & RADEON_IS_IGP))
if (!radeon_card_posted(rdev))
return false;
@ -170,7 +170,7 @@ static bool radeon_read_bios(struct radeon_device *rdev)
printf(": can't map PCI ROM (%d)\n", rc);
return false;
}
rdev->bios = kmalloc(size, GFP_KERNEL);
bus_space_read_region_1(rdev->memt, romh, 0, rdev->bios, size);
bus_space_unmap(rdev->memt, romh, size);
@ -224,7 +224,7 @@ static bool radeon_read_platform_bios(struct radeon_device *rdev)
bus_size_t size = 256 * 1024; /* ??? */
uint8_t *found = NULL;
int i;
if (!(rdev->flags & RADEON_IS_IGP))
if (!radeon_card_posted(rdev))
return false;
@ -244,7 +244,7 @@ static bool radeon_read_platform_bios(struct radeon_device *rdev)
found = bios + i;
break;
}
}
if (found == NULL) {
DRM_ERROR("bios size zero or checksum mismatch\n");
@ -524,7 +524,7 @@ static bool r600_read_disabled_bios(struct radeon_device *rdev)
uint32_t ctxsw_vid_lower_gpio_cntl;
uint32_t lower_gpio_enable;
bool r;
/*
* Some machines with RV610 running amd64 pass initial checks but later
* fail atombios specific checks. Return early here so the bios will be

4
sys/dev/pci/drm/radeon/radeon_drv.c
View file

@ -726,7 +726,7 @@ const struct cfattach radeondrm_ca = {
radeondrm_detach_kms, radeondrm_activate_kms
};
struct cfdriver radeondrm_cd = {
struct cfdriver radeondrm_cd = {
NULL, "radeondrm", DV_DULL
};
@ -757,7 +757,7 @@ radeondrm_detach_kms(struct device *self, int flags)
#endif
radeon_acpi_fini(rdev);
radeon_modeset_fini(rdev);
radeon_device_fini(rdev);

1
sys/dev/pci/drm/radeon/radeon_fence.c
View file

@ -1085,7 +1085,6 @@ static signed long radeon_fence_default_wait(struct dma_fence *f, bool intr,
break;
}
KASSERT(sch_ident != NULL);
t = schedule_timeout(t);
if (t > 0 && intr && signal_pending(current))

2
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
View file

@ -322,7 +322,7 @@ static void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
*/
if (rdev->flags & RADEON_SINGLE_CRTC)
crtc_ext_cntl = RADEON_CRTC_CRT_ON;
switch (mode) {
case DRM_MODE_DPMS_ON:
radeon_crtc->enabled = true;

2
sys/dev/pci/drm/radeon/radeon_pm.c
View file

@ -738,7 +738,7 @@ static ssize_t radeon_hwmon_show_sclk(struct device *dev,
if (rdev->asic->dpm.get_current_sclk)
sclk = radeon_dpm_get_current_sclk(rdev);
/* Value returned by dpm is in 10 KHz units, need to convert it into Hz
/* Value returned by dpm is in 10 KHz units, need to convert it into Hz
for hwmon */
sclk *= 10000;

2
sys/dev/pci/drm/radeon/radeon_sa.c
View file

@ -360,7 +360,7 @@ int radeon_sa_bo_new(struct radeon_device *rdev,
/* if we have nothing to wait for block */
if (r == -ENOENT) {
r = wait_event_interruptible_locked(
sa_manager->wq,
sa_manager->wq,
radeon_sa_event(sa_manager, size, align)
);
}

10
sys/dev/pci/drm/radeon/rs690.c
View file

@ -175,25 +175,25 @@ static void rs690_mc_init(struct radeon_device *rdev)
rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
}
/* Use K8 direct mapping for fast fb access. */
/* Use K8 direct mapping for fast fb access. */
rdev->fastfb_working = false;
h_addr = G_00005F_K8_ADDR_EXT(RREG32_MC(R_00005F_MC_MISC_UMA_CNTL));
l_addr = RREG32_MC(R_00001E_K8_FB_LOCATION);
k8_addr = ((unsigned long long)h_addr) << 32 | l_addr;
#if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE)
if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL)
if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL)
#endif
{
/* FastFB shall be used with UMA memory. Here it is simply disabled when sideport
/* FastFB shall be used with UMA memory. Here it is simply disabled when sideport
* memory is present.
*/
if (!rdev->mc.igp_sideport_enabled && radeon_fastfb == 1) {
DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n",
DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n",
(unsigned long long)rdev->mc.aper_base, k8_addr);
rdev->mc.aper_base = (resource_size_t)k8_addr;
rdev->fastfb_working = true;
}
}
}
rs690_pm_info(rdev);
radeon_vram_location(rdev, &rdev->mc, base);

8
sys/dev/pci/drm/radeon/rv740_dpm.c
View file

@ -249,8 +249,12 @@ int rv740_populate_mclk_value(struct radeon_device *rdev,
ASIC_INTERNAL_MEMORY_SS, vco_freq)) {
u32 reference_clock = rdev->clock.mpll.reference_freq;
u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div);
u32 clk_s = reference_clock * 5 / (decoded_ref * ss.rate);
u32 clk_v = 0x40000 * ss.percentage *
u32 clk_s, clk_v;
if (!decoded_ref)
return -EINVAL;
clk_s = reference_clock * 5 / (decoded_ref * ss.rate);
clk_v = 0x40000 * ss.percentage *
(dividers.whole_fb_div + (dividers.frac_fb_div / 8)) / (clk_s * 10000);
mpll_ss1 &= ~CLKV_MASK;

14
sys/dev/pci/if_ix.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: if_ix.c,v 1.198 2023/07/08 09:01:30 jmatthew Exp $ */
/* $OpenBSD: if_ix.c,v 1.200 2023/07/18 16:01:20 bluhm Exp $ */
/******************************************************************************
@ -37,6 +37,12 @@
#include <dev/pci/if_ix.h>
#include <dev/pci/ixgbe_type.h>
/*
* Our TCP/IP Stack could not handle packets greater than MAXMCLBYTES.
* This interface could not handle packets greater than IXGBE_TSO_SIZE.
*/
CTASSERT(MAXMCLBYTES <= IXGBE_TSO_SIZE);
/*********************************************************************
* Driver version
*********************************************************************/
@ -1925,8 +1931,10 @@ ixgbe_setup_interface(struct ix_softc *sc)
ifp->if_capabilities |= IFCAP_CSUM_IPv4;
ifp->if_capabilities |= IFCAP_TSOv4 | IFCAP_TSOv6;
if (sc->hw.mac.type != ixgbe_mac_82598EB)
if (sc->hw.mac.type != ixgbe_mac_82598EB) {
ifp->if_xflags |= IFXF_LRO;
ifp->if_capabilities |= IFCAP_LRO;
}
/*
* Specify the media types supported by this sc and register
@ -2263,7 +2271,7 @@ ixgbe_allocate_transmit_buffers(struct tx_ring *txr)
/* Create the descriptor buffer dma maps */
for (i = 0; i < sc->num_tx_desc; i++) {
txbuf = &txr->tx_buffers[i];
error = bus_dmamap_create(txr->txdma.dma_tag, IXGBE_TSO_SIZE,
error = bus_dmamap_create(txr->txdma.dma_tag, MAXMCLBYTES,
sc->num_segs, PAGE_SIZE, 0,
BUS_DMA_NOWAIT, &txbuf->map);

25
sys/dev/pci/if_ixl.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: if_ixl.c,v 1.87 2023/02/06 20:27:45 jan Exp $ */
/* $OpenBSD: if_ixl.c,v 1.88 2023/07/19 20:22:05 jan Exp $ */
/*
* Copyright (c) 2013-2015, Intel Corporation
@ -1274,6 +1274,7 @@ struct ixl_softc {
unsigned int sc_atq_prod;
unsigned int sc_atq_cons;
struct mutex sc_atq_mtx;
struct ixl_dmamem sc_arq;
struct task sc_arq_task;
struct ixl_aq_bufs sc_arq_idle;
@ -1723,6 +1724,8 @@ ixl_attach(struct device *parent, struct device *self, void *aux)
/* initialise the adminq */
mtx_init(&sc->sc_atq_mtx, IPL_NET);
if (ixl_dmamem_alloc(sc, &sc->sc_atq,
sizeof(struct ixl_aq_desc) * IXL_AQ_NUM, IXL_AQ_ALIGN) != 0) {
printf("\n" "%s: unable to allocate atq\n", DEVNAME(sc));
@ -3599,7 +3602,7 @@ ixl_atq_post(struct ixl_softc *sc, struct ixl_atq *iatq)
struct ixl_aq_desc *atq, *slot;
unsigned int prod;
/* assert locked */
mtx_enter(&sc->sc_atq_mtx);
atq = IXL_DMA_KVA(&sc->sc_atq);
prod = sc->sc_atq_prod;
@ -3618,6 +3621,8 @@ ixl_atq_post(struct ixl_softc *sc, struct ixl_atq *iatq)
prod &= IXL_AQ_MASK;
sc->sc_atq_prod = prod;
ixl_wr(sc, sc->sc_aq_regs->atq_tail, prod);
mtx_leave(&sc->sc_atq_mtx);
}
static void
@ -3628,11 +3633,15 @@ ixl_atq_done(struct ixl_softc *sc)
unsigned int cons;
unsigned int prod;
mtx_enter(&sc->sc_atq_mtx);
prod = sc->sc_atq_prod;
cons = sc->sc_atq_cons;
if (prod == cons)
if (prod == cons) {
mtx_leave(&sc->sc_atq_mtx);
return;
}
atq = IXL_DMA_KVA(&sc->sc_atq);
@ -3645,6 +3654,7 @@ ixl_atq_done(struct ixl_softc *sc)
if (!ISSET(slot->iaq_flags, htole16(IXL_AQ_DD)))
break;
KASSERT(slot->iaq_cookie != 0);
iatq = (struct ixl_atq *)slot->iaq_cookie;
iatq->iatq_desc = *slot;
@ -3661,6 +3671,8 @@ ixl_atq_done(struct ixl_softc *sc)
BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
sc->sc_atq_cons = cons;
mtx_leave(&sc->sc_atq_mtx);
}
static void
@ -3691,6 +3703,8 @@ ixl_atq_poll(struct ixl_softc *sc, struct ixl_aq_desc *iaq, unsigned int tm)
unsigned int prod;
unsigned int t = 0;
mtx_enter(&sc->sc_atq_mtx);
atq = IXL_DMA_KVA(&sc->sc_atq);
prod = sc->sc_atq_prod;
slot = atq + prod;
@ -3712,8 +3726,10 @@ ixl_atq_poll(struct ixl_softc *sc, struct ixl_aq_desc *iaq, unsigned int tm)
while (ixl_rd(sc, sc->sc_aq_regs->atq_head) != prod) {
delaymsec(1);
if (t++ > tm)
if (t++ > tm) {
mtx_leave(&sc->sc_atq_mtx);
return (ETIMEDOUT);
}
}
bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq),
@ -3724,6 +3740,7 @@ ixl_atq_poll(struct ixl_softc *sc, struct ixl_aq_desc *iaq, unsigned int tm)
sc->sc_atq_cons = prod;
mtx_leave(&sc->sc_atq_mtx);
return (0);
}

7
sys/dev/pci/if_myx.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: if_myx.c,v 1.117 2023/06/28 08:23:25 claudio Exp $ */
/* $OpenBSD: if_myx.c,v 1.118 2023/07/14 07:07:08 claudio Exp $ */
/*
* Copyright (c) 2007 Reyk Floeter <reyk@openbsd.org>
@ -1377,7 +1377,6 @@ myx_down(struct myx_softc *sc)
struct ifnet *ifp = &sc->sc_ac.ac_if;
volatile struct myx_status *sts = sc->sc_sts;
bus_dmamap_t map = sc->sc_sts_dma.mxm_map;
struct sleep_state sls;
struct myx_cmd mc;
int s;
int ring;
@ -1397,9 +1396,9 @@ myx_down(struct myx_softc *sc)
(void)myx_cmd(sc, MYXCMD_SET_IFDOWN, &mc, NULL);
while (sc->sc_state != MYX_S_OFF) {
sleep_setup(&sls, sts, PWAIT, "myxdown");
sleep_setup(sts, PWAIT, "myxdown");
membar_consumer();
sleep_finish(&sls, PWAIT, 0, sc->sc_state != MYX_S_OFF);
sleep_finish(0, sc->sc_state != MYX_S_OFF);
}
s = splnet();

4
sys/dev/pci/if_rtwn.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: if_rtwn.c,v 1.40 2022/04/21 21:03:03 stsp Exp $ */
/* $OpenBSD: if_rtwn.c,v 1.41 2023/07/14 14:28:47 kevlo Exp $ */
/*-
* Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
@ -1022,7 +1022,7 @@ rtwn_tx(void *cookie, struct mbuf *m, struct ieee80211_node *ni)
/* Fill Tx descriptor. */
txd = &tx_ring->desc[tx_ring->cur];
if (htole32(txd->txdw0) & R92C_RXDW0_OWN) {
if (htole32(txd->txdw0) & R92C_TXDW0_OWN) {
m_freem(m);
return (ENOBUFS);
}

4
sys/dev/usb/ehci.c
View file

@ -1248,11 +1248,11 @@ ehci_dump_sqtds(struct ehci_soft_qtd *sqtd)
void
ehci_dump_sqtd(struct ehci_soft_qtd *sqtd)
{
usb_syncmem(&sqtd->dma, sqtd->offs,
usb_syncmem(&sqtd->dma, sqtd->offs,
sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr);
ehci_dump_qtd(&sqtd->qtd);
usb_syncmem(&sqtd->dma, sqtd->offs,
usb_syncmem(&sqtd->dma, sqtd->offs,
sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD);
}

2
sys/dev/usb/ehcireg.h
View file

@ -167,7 +167,7 @@
#define EHCI_USBMODE_CM_M 0x00000003
#define EHCI_USBMODE_CM_IDLE 0x00000000
#define EHCI_USBMODE_CM_DEVICE 0x00000002
#define EHCI_USBMODE_CM_HOST 0x00000003
#define EHCI_USBMODE_CM_HOST 0x00000003
#define EHCI_FLALIGN_ALIGN 0x1000

2
sys/dev/usb/files.usb
View file

@ -236,7 +236,7 @@ attach axen at uhub
file dev/usb/if_axen.c axen
# SMSC LAN95xx
device smsc: ether, ifnet, mii, ifmedia
device smsc: ether, ifnet, mii, ifmedia
attach smsc at uhub
file dev/usb/if_smsc.c smsc

14
sys/dev/usb/if_athn_usb.c
View file

@ -618,7 +618,7 @@ athn_usb_do_async(struct athn_usb_softc *usc,
printf("%s: host cmd queue overrun\n", usc->usb_dev.dv_xname);
return; /* XXX */
}
s = splusb();
cmd = &ring->cmd[ring->cur];
cmd->cb = cb;
@ -897,7 +897,7 @@ athn_usb_wmi_xcmd(struct athn_usb_softc *usc, uint16_t cmd_id, void *ibuf,
}
usc->obuf = obuf;
usc->wait_cmd_id = cmd_id;
/*
/*
* Wait for WMI command complete interrupt. In case it does not fire
* wait until the USB transfer times out to avoid racing the transfer.
*/
@ -911,7 +911,7 @@ athn_usb_wmi_xcmd(struct athn_usb_softc *usc, uint16_t cmd_id, void *ibuf,
}
}
/*
/*
* Both the WMI command and transfer are done or have timed out.
* Allow other threads to enter this function and use data->xfer.
*/
@ -1260,7 +1260,7 @@ athn_usb_newauth(struct ieee80211com *ic, struct ieee80211_node *ni,
return ENOSPC;
}
/*
/*
* In a process context, try to add this node to the
* firmware table and confirm the AUTH request.
*/
@ -1280,7 +1280,7 @@ athn_usb_node_free(struct ieee80211com *ic, struct ieee80211_node *ni)
struct athn_usb_softc *usc = ic->ic_softc;
struct athn_node *an = (struct athn_node *)ni;
/*
/*
* Remove the node from the firmware table in a process context.
* Pass an index rather than the pointer which we will free.
*/
@ -1378,7 +1378,7 @@ athn_usb_clean_nodes(void *arg, struct ieee80211_node *ni)
struct ieee80211com *ic = &usc->sc_sc.sc_ic;
struct athn_node *an = (struct athn_node *)ni;
/*
/*
* Don't remove the default node (used for management frames).
* Nodes which are not in the firmware table also have index zero.
*/
@ -1392,7 +1392,7 @@ athn_usb_clean_nodes(void *arg, struct ieee80211_node *ni)
return;
}
/*
/*
* Kick off inactive associated nodes. This won't help
* immediately but will help if the new STA retries later.
*/

6
sys/dev/usb/if_athn_usb.h
View file

@ -135,7 +135,7 @@ struct ar_htc_target_rate {
#define AR_RC_SGI_FLAG 0x00000004
#define AR_RC_HT_FLAG 0x00000008
#define AR_RC_STBC_FLAG 0x00000030 /* 2 bits */
#define AR_RC_WEP_TKIP_FLAG 0x00000100
#define AR_RC_WEP_TKIP_FLAG 0x00000100
struct ar_htc_rateset lg_rates;
struct ar_htc_rateset ht_rates;
@ -181,7 +181,7 @@ struct ar_htc_cap_target {
struct ar_wmi_evt_txstatus {
uint8_t cookie;
/*
/*
* Legacy rates are indicated as rate array indices.
* HT rates are indicated as MCS indices.
*/
@ -475,7 +475,7 @@ struct athn_usb_softc {
uint8_t ep_mgmt;
uint8_t ep_data[EDCA_NUM_AC];
/*
/*
* Firmware cannot handle more than 8 STAs.
* We use a bitmask to keep track of available slots in the firmware's
* node array. A 1 bit at index N, as determined by ffs(3), means the

24
sys/dev/usb/if_atureg.h
View file

@ -161,7 +161,7 @@ struct atu_cdata {
struct atu_list_head atu_tx_free;
u_int8_t atu_tx_inuse;
u_int8_t atu_tx_last_idx;
u_int8_t atu_tx_last_idx;
};
#define MAX_SSID_LEN 32
@ -190,11 +190,11 @@ struct atu_softc {
struct atu_cdata atu_cdata;
struct timeval atu_rx_notice;
u_int8_t atu_bssid[ETHER_ADDR_LEN];
enum atu_radio_type atu_radio;
u_int16_t atu_quirk;
u_int8_t atu_channel;
u_int16_t atu_desired_channel;
u_int8_t atu_mode;
@ -297,7 +297,7 @@ struct atu_cmd_card_config {
uByte Cmd;
uByte Reserved;
uWord Size;
uByte ExcludeUnencrypted;
uByte PromiscuousMode;
uByte ShortRetryLimit;
@ -321,7 +321,7 @@ struct atu_cmd_do_scan {
uByte Cmd;
uByte Reserved;
uWord Size;
uByte BSSID[ETHER_ADDR_LEN];
uByte SSID[MAX_SSID_LEN];
uByte ScanType;
@ -330,7 +330,7 @@ struct atu_cmd_do_scan {
uWord MinChannelTime;
uWord MaxChannelTime;
uByte SSID_Len;
uByte InternationalScan;
uByte InternationalScan;
} __packed;
#define ATU_SCAN_ACTIVE 0x00
@ -341,7 +341,7 @@ struct atu_cmd_join {
uByte Cmd;
uByte Reserved;
uWord Size;
uByte bssid[ETHER_ADDR_LEN];
uByte essid[32];
uByte bss_type;
@ -356,13 +356,13 @@ struct atu_cmd_start_ibss {
uByte Cmd;
uByte Reserved;
uWord Size;
uByte BSSID[ETHER_ADDR_LEN];
uByte SSID[32];
uByte BSSType;
uByte Channel;
uByte BSSType;
uByte Channel;
uByte SSIDSize;
uByte Res[3];
uByte Res[3];
} __packed;
/*
@ -406,7 +406,7 @@ struct atu_fw {
u_int8_t patch;
u_int8_t build;
} __packed;
/*
* The header the AT76c503 puts in front of RX packets (for both management &
* data)

2
sys/dev/usb/if_axe.c
View file

@ -545,7 +545,7 @@ axe_ax88178_init(struct axe_softc *sc)
AXE_GPIO_WRITE(AXE_GPIO1_EN, 30);
AXE_GPIO_WRITE(AXE_GPIO1_EN | AXE_GPIO1, 30);
} else {
val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN :
val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN :
AXE_GPIO1 | AXE_GPIO1_EN;
AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, 30);
AXE_GPIO_WRITE(val | AXE_GPIO2_EN, 300);

26
sys/dev/usb/if_axen.c
View file

@ -382,7 +382,7 @@ axen_iff(struct axen_softc *sc)
}
}
axen_cmd(sc, AXEN_CMD_MAC_WRITE_FILTER, 8, AXEN_FILTER_MULTI,
axen_cmd(sc, AXEN_CMD_MAC_WRITE_FILTER, 8, AXEN_FILTER_MULTI,
(void *)&hashtbl);
USETW(wval, rxmode);
axen_cmd(sc, AXEN_CMD_MAC_WRITE2, 2, AXEN_MAC_RXCTL, &wval);
@ -394,7 +394,7 @@ axen_reset(struct axen_softc *sc)
{
if (usbd_is_dying(sc->axen_udev))
return;
axen_ax88179_init(sc);
/* Wait a little while for the chip to get its brains in order. */
@ -625,19 +625,19 @@ axen_attach(struct device *parent, struct device *self, void *aux)
/* decide on what our bufsize will be */
switch (sc->axen_udev->speed) {
case USB_SPEED_FULL:
sc->axen_bufsz = AXEN_BUFSZ_LS * 1024;
sc->axen_bufsz = AXEN_BUFSZ_LS * 1024;
break;
case USB_SPEED_HIGH:
sc->axen_bufsz = AXEN_BUFSZ_HS * 1024;
sc->axen_bufsz = AXEN_BUFSZ_HS * 1024;
break;
case USB_SPEED_SUPER:
sc->axen_bufsz = AXEN_BUFSZ_SS * 1024;
sc->axen_bufsz = AXEN_BUFSZ_SS * 1024;
break;
default:
printf("%s: not supported usb bus type", sc->axen_dev.dv_xname);
return;
}
/* Find endpoints. */
for (i = 0; i < id->bNumEndpoints; i++) {
ed = usbd_interface2endpoint_descriptor(sc->axen_iface, i);
@ -914,7 +914,7 @@ axen_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status)
goto done;
}
/*
/*
* buffer map
* [packet #0]...[packet #n][pkt hdr#0]..[pkt hdr#n][recv_hdr]
* each packet has 0xeeee as pseudo header..
@ -945,9 +945,9 @@ axen_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status)
*/
#if 1 /* XXX: paranoiac check. need to remove later */
#define AXEN_MAX_PACKED_PACKET 200
#define AXEN_MAX_PACKED_PACKET 200
if (pkt_count > AXEN_MAX_PACKED_PACKET) {
DPRINTF(("Too many packets (%d) in a transaction, discard.\n",
DPRINTF(("Too many packets (%d) in a transaction, discard.\n",
pkt_count));
goto done;
}
@ -988,7 +988,7 @@ axen_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status)
#ifdef AXEN_TOE
/* checksum err */
if ((pkt_hdr & AXEN_RXHDR_L3CSUM_ERR) ||
if ((pkt_hdr & AXEN_RXHDR_L3CSUM_ERR) ||
(pkt_hdr & AXEN_RXHDR_L4CSUM_ERR)) {
printf("%s: checksum err (pkt#%d)\n",
sc->axen_dev.dv_xname, pkt_count);
@ -998,11 +998,11 @@ axen_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status)
}
int l4_type;
l4_type = (pkt_hdr & AXEN_RXHDR_L4_TYPE_MASK) >>
l4_type = (pkt_hdr & AXEN_RXHDR_L4_TYPE_MASK) >>
AXEN_RXHDR_L4_TYPE_OFFSET;
if ((l4_type == AXEN_RXHDR_L4_TYPE_TCP) ||
(l4_type == AXEN_RXHDR_L4_TYPE_UDP))
(l4_type == AXEN_RXHDR_L4_TYPE_UDP))
m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK |
M_UDP_CSUM_IN_OK;
#endif
@ -1013,7 +1013,7 @@ axen_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status)
nextpkt:
/*
* prepare next packet
* prepare next packet
* as each packet will be aligned 8byte boundary,
* need to fix up the start point of the buffer.
*/

16
sys/dev/usb/if_axenreg.h
View file

@ -20,7 +20,7 @@
#define AXEN_REV_UA2 1
/* receive header */
/*
/*
* +-multicast/broadcast
* | +-rx_ok
* | | ++-----L3_type (1:ipv4, 0/2:ipv6)
@ -84,7 +84,7 @@
#define AXEN_CMD_CMD(x) ((x) & 0x00FF)
/* ---MAC--- */
/* 1byte cmd */
/* 1byte cmd */
#define AXEN_CMD_MAC_READ 0x1001
#define AXEN_CMD_MAC_WRITE 0x1101
@ -141,7 +141,7 @@
#define AXEN_PAUSE_LOW_WATERMARK 0x55
/* 2byte cmd */
/* 2byte cmd */
#define AXEN_CMD_MAC_READ2 0x2001
#define AXEN_CMD_MAC_WRITE2 0x2101
@ -149,7 +149,7 @@
#define AXEN_RXCTL_STOP 0x0000
#define AXEN_RXCTL_PROMISC 0x0001
#define AXEN_RXCTL_ACPT_ALL_MCAST 0x0002
#define AXEN_RXCTL_HA8B 0x0004
#define AXEN_RXCTL_HA8B 0x0004
#define AXEN_RXCTL_AUTOB 0x0008
#define AXEN_RXCTL_ACPT_BCAST 0x0010
#define AXEN_RXCTL_ACPT_PHY_MCAST 0x0020
@ -176,22 +176,22 @@
#define AXEN_CMD_EEPROM_READ 0x2004
#define AXEN_EEPROM_STAT 0x43
/* 5byte cmd */
/* 5byte cmd */
#define AXEN_CMD_MAC_SET_RXSR 0x5101
#define AXEN_RX_BULKIN_QCTRL 0x2e
/* 6byte cmd */
/* 6byte cmd */
#define AXEN_CMD_MAC_READ_ETHER 0x6001
#define AXEN_CMD_MAC_WRITE_ETHER 0x6101
#define AXEN_CMD_MAC_NODE_ID 0x10
/* 8byte cmd */
/* 8byte cmd */
#define AXEN_CMD_MAC_READ_FILTER 0x8001
#define AXEN_CMD_MAC_WRITE_FILTER 0x8101
#define AXEN_FILTER_MULTI 0x16
/* ---PHY--- */
/* 2byte cmd */
/* 2byte cmd */
#define AXEN_CMD_MII_READ_REG 0x2002
#define AXEN_CMD_MII_WRITE_REG 0x2102

10
sys/dev/usb/if_cdce.c
View file

@ -225,7 +225,7 @@ cdce_attach(struct device *parent, struct device *self, void *aux)
}
switch(desc->bDescriptorSubtype) {
case UDESCSUB_CDC_UNION:
ud = (struct usb_cdc_union_descriptor *)desc;
ud = (struct usb_cdc_union_descriptor *)desc;
if ((sc->cdce_flags & CDCE_SWAPUNION) == 0 &&
ud->bMasterInterface == ctl_ifcno)
data_ifcno = ud->bSlaveInterface[0];
@ -290,10 +290,10 @@ cdce_attach(struct device *parent, struct device *self, void *aux)
for (j = 0; j < numalts; j++) {
if (usbd_set_interface(sc->cdce_data_iface, j)) {
printf("%s: interface alternate setting %d failed\n",
printf("%s: interface alternate setting %d failed\n",
sc->cdce_dev.dv_xname, j);
return;
}
}
/* Find endpoints. */
id = usbd_get_interface_descriptor(sc->cdce_data_iface);
sc->cdce_bulkin_no = sc->cdce_bulkout_no = -1;
@ -330,7 +330,7 @@ cdce_attach(struct device *parent, struct device *self, void *aux)
goto found;
}
}
if (sc->cdce_bulkin_no == -1) {
printf("%s: could not find data bulk in\n",
sc->cdce_dev.dv_xname);
@ -385,7 +385,7 @@ found:
int
cdce_detach(struct device *self, int flags)
{
struct cdce_softc *sc = (struct cdce_softc *)self;
struct cdce_softc *sc = (struct cdce_softc *)self;
struct ifnet *ifp = GET_IFP(sc);
int s;

2
sys/dev/usb/xhci.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: xhci.c,v 1.128 2023/01/01 21:45:40 kettenis Exp $ */
/* $OpenBSD: xhci.c,v 1.130 2023/07/20 09:43:00 claudio Exp $ */
/*
* Copyright (c) 2014-2015 Martin Pieuchot