sync code with last fixes and improvements from OpenBSD

sys/arch/amd64/amd64/cpu.c

@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpu.c,v 1.169 2023/06/15 22:18:06 cheloha Exp $	*/
+/*	$OpenBSD: cpu.c,v 1.170 2023/07/10 03:32:10 guenther Exp $	*/
 /* $NetBSD: cpu.c,v 1.1 2003/04/26 18:39:26 fvdl Exp $ */
 
 /*-
@@ -162,6 +162,7 @@ int cpu_perf_edx = 0;		/* cpuid(0xa).edx */
 int cpu_apmi_edx = 0;		/* cpuid(0x80000007).edx */
 int ecpu_ecxfeature = 0;	/* cpuid(0x80000001).ecx */
 int cpu_meltdown = 0;
+int cpu_use_xsaves = 0;
 
 void
 replacesmap(void)
@@ -699,10 +700,9 @@ cpu_attach(struct device *parent, struct device *self, void *aux)
 }
 
 static void
-replacexsave(void)
+replacexsave(int xsave_ext)
 {
-	extern long _xrstor, _xsave, _xsaveopt;
-	u_int32_t eax, ebx, ecx, edx;
+	extern long _xrstor, _xrstors, _xsave, _xsaves, _xsaveopt;
 	static int replacedone = 0;
 	int s;
 
@@ -710,12 +710,13 @@ replacexsave(void)
 		return;
 	replacedone = 1;
 
-	/* find out whether xsaveopt is supported */
-	CPUID_LEAF(0xd, 1, eax, ebx, ecx, edx);
 	s = splhigh();
+	codepatch_replace(CPTAG_XRSTORS,
+	    (xsave_ext & XSAVE_XSAVES) ? &_xrstors : &_xrstor, 4);
 	codepatch_replace(CPTAG_XRSTOR, &_xrstor, 4);
 	codepatch_replace(CPTAG_XSAVE,
-	    (eax & XSAVE_XSAVEOPT) ? &_xsaveopt : &_xsave, 4);
+	    (xsave_ext & XSAVE_XSAVES) ? &_xsaves :
+	    (xsave_ext & XSAVE_XSAVEOPT) ? &_xsaveopt : &_xsave, 4);
 	splx(s);
 }
 
@@ -764,20 +765,46 @@ cpu_init(struct cpu_info *ci)
 			KASSERT(ebx == fpu_save_len);
 		}
 
-		replacexsave();
+		/* check for xsaves, xsaveopt, and supervisor features */
+		CPUID_LEAF(0xd, 1, eax, ebx, ecx, edx);
+		/* Disable XSAVES on AMD family 17h due to Erratum 1386 */
+		if (!strcmp(cpu_vendor, "AuthenticAMD") &&
+		    ci->ci_family == 0x17) {
+			eax &= ~XSAVE_XSAVES;
+		}
+		if (eax & XSAVE_XSAVES) {
+#ifndef SMALL_KERNEL
+			if (ci->ci_feature_sefflags_edx & SEFF0EDX_IBT)
+				xsave_mask |= ecx & XFEATURE_CET_U;
+#endif
+			if (xsave_mask & XFEATURE_XSS_MASK) {
+				wrmsr(MSR_XSS, xsave_mask & XFEATURE_XSS_MASK);
+				CPUID_LEAF(0xd, 1, eax, ebx, ecx, edx);
+				KASSERT(ebx <= sizeof(struct savefpu));
+			}
+			if (CPU_IS_PRIMARY(ci))
+				cpu_use_xsaves = 1;
+		}
+
+		replacexsave(eax);
 	}
 
-	/* Give proc0 a clean FPU save area */
-	sfp = &proc0.p_addr->u_pcb.pcb_savefpu;
-	memset(sfp, 0, fpu_save_len);
-	sfp->fp_fxsave.fx_fcw = __INITIAL_NPXCW__;
-	sfp->fp_fxsave.fx_mxcsr = __INITIAL_MXCSR__;
-	fpureset();
-	if (xsave_mask) {
-		/* must not use xsaveopt here */
-		xsave(sfp, xsave_mask);
-	} else
-		fxsave(sfp);
+	if (CPU_IS_PRIMARY(ci)) {
+		/* Clean our FPU save area */
+		sfp = fpu_cleandata;
+		memset(sfp, 0, fpu_save_len);
+		sfp->fp_fxsave.fx_fcw = __INITIAL_NPXCW__;
+		sfp->fp_fxsave.fx_mxcsr = __INITIAL_MXCSR__;
+		xrstor_user(sfp, xsave_mask);
+		if (cpu_use_xsaves || !xsave_mask)
+			fpusave(sfp);
+		else {
+			/* must not use xsaveopt here */
+			xsave(sfp, xsave_mask);
+		}
+	} else {
+		fpureset();
+	}
 
 #if NVMM > 0
 	/* Re-enable VMM if needed */

sys/arch/amd64/amd64/locore.S

@@ -1,4 +1,4 @@
-/*	$OpenBSD: locore.S,v 1.135 2023/07/05 18:23:10 anton Exp $	*/
+/*	$OpenBSD: locore.S,v 1.136 2023/07/10 03:32:10 guenther Exp $	*/
 /*	$NetBSD: locore.S,v 1.13 2004/03/25 18:33:17 drochner Exp $	*/
 
 /*
@@ -342,7 +342,7 @@ switch_exited:
 #endif
 	CODEPATCH_START
 	fxrstor64	(%rdi)
-	CODEPATCH_END(CPTAG_XRSTOR)
+	CODEPATCH_END(CPTAG_XRSTORS)
 	andl	$~CPUPF_USERXSTATE,CPUVAR(PFLAGS)
 
 .Lxstate_reset:
@@ -680,7 +680,7 @@ KUTEXT_PAGE_END
 	/* untouched state so can't fault */
 	CODEPATCH_START
 	fxrstor64	(%rdi)
-	CODEPATCH_END(CPTAG_XRSTOR)
+	CODEPATCH_END(CPTAG_XRSTORS)
 #if PCB_SAVEFPU != 0
 	subq	$PCB_SAVEFPU,%rdi
 #endif
@@ -868,10 +868,14 @@ KTEXT_PAGE_END
 #if PCB_SAVEFPU != 0
 	addq	$PCB_SAVEFPU,%rdi
 #endif
-	movq	xsave_mask(%rip),%rsi
-	call	xrstor_user
-	testl	%eax,%eax
-	jnz	.Lintr_xrstor_faulted
+	movq	xsave_mask(%rip),%rdx
+	movl	%edx,%eax
+	shrq	$32, %rdx
+	CODEPATCH_START
+	fxrstor64	(%rdi)
+	CODEPATCH_END(CPTAG_XRSTORS)
+	//testl	%eax,%eax
+	//jnz	.Lintr_xrstor_faulted
 .Lintr_restore_fsbase:		/* CPU doesn't have curproc's FS.base */
 	orl	$CPUPF_USERSEGS,CPUVAR(PFLAGS)
 	movq	CPUVAR(CURPCB),%rdx
@@ -894,7 +898,7 @@ KTEXT_PAGE_END
 #endif
 	CODEPATCH_START
 	fxrstor64	(%rdi)
-	CODEPATCH_END(CPTAG_XRSTOR)
+	CODEPATCH_END(CPTAG_XRSTORS)
 	movq	$T_PROTFLT,TF_TRAPNO(%rsp)
 	jmp	recall_trap
 
@@ -945,7 +949,6 @@ NENTRY(intr_fast_exit)
 	testq	$PSL_I,%rdx
 	jnz	.Lintr_exit_not_blocked
 #endif /* DIAGNOSTIC */
-	call	pku_xonly	/* XXX guenther disapproves, but foo3 locks */
 	movq	TF_RDI(%rsp),%rdi
 	movq	TF_RSI(%rsp),%rsi
 	movq	TF_R8(%rsp),%r8
@@ -992,8 +995,14 @@ END(intr_fast_exit)
 
 /*
  * FPU/"extended CPU state" handling
+ *	void xrstor_kern(sfp, mask)
+ *		using first of xrstors/xrstor/fxrstor, load given state
+ *		which is assumed to be trusted: i.e., unaltered from
+ *		xsaves/xsaveopt/xsave/fxsave by kernel
  * 	int xrstor_user(sfp, mask)
- *		load given state, returns 0/1 if okay/it trapped
+ *		using first of xrstor/fxrstor, load given state which might
+ *		not be trustable: #GP faults will be caught; returns 0/1 if
+ *		okay/it trapped.
  *	void fpusave(sfp)
  *		save current state, but retain it in the FPU
  *	void fpusavereset(sfp)
@@ -1002,6 +1011,19 @@ END(intr_fast_exit)
  *		load specified %xcr# register, returns 0/1 if okay/it trapped
  */
 
+ENTRY(xrstor_kern)
+	RETGUARD_SETUP(xrstor_kern, r11)
+	movq	%rsi, %rdx
+	movl	%esi, %eax
+	shrq	$32, %rdx
+	CODEPATCH_START
+	fxrstor64	(%rdi)
+	CODEPATCH_END(CPTAG_XRSTORS)
+	RETGUARD_CHECK(xrstor_kern, r11)
+	ret
+	lfence
+END(xrstor_kern)
+
 ENTRY(xrstor_user)
 	RETGUARD_SETUP(xrstor_user, r11)
 	movq	%rsi, %rdx
@@ -1050,7 +1072,7 @@ ENTRY(fpusavereset)
 #endif
 	CODEPATCH_START
 	fxrstor64	(%rdi)
-	CODEPATCH_END(CPTAG_XRSTOR)
+	CODEPATCH_END(CPTAG_XRSTORS)
 	RETGUARD_CHECK(fpusavereset, r11)
 	ret
 	lfence
@@ -1081,9 +1103,17 @@ END(xsetbv_user)
 _xrstor:
 	xrstor64	(%rdi)
 
+	.globl	_xrstors
+_xrstors:
+	xrstors64	(%rdi)
+
 	.globl	_xsave
 _xsave:
-	xsave64	(%rdi)
+	xsave64		(%rdi)
+
+	.globl	_xsaves
+_xsaves:
+	xsaves64	(%rdi)
 
 	.globl	_xsaveopt
 _xsaveopt:

sys/arch/amd64/amd64/machdep.c

@@ -1,4 +1,4 @@
-/*	$OpenBSD: machdep.c,v 1.284 2022/11/29 21:41:39 guenther Exp $	*/
+/*	$OpenBSD: machdep.c,v 1.285 2023/07/10 03:32:10 guenther Exp $	*/
 /*	$NetBSD: machdep.c,v 1.3 2003/05/07 22:58:18 fvdl Exp $	*/
 
 /*-
@@ -564,6 +564,63 @@ cpu_sysctl(int *name, u_int namelen, void *oldp, size_t *oldlenp, void *newp,
 	/* NOTREACHED */
 }
 
+static inline void
+maybe_enable_user_cet(struct proc *p)
+{
+#ifndef SMALL_KERNEL
+	/* Enable indirect-branch tracking if present and not disabled */
+	if ((xsave_mask & XFEATURE_CET_U) &&
+	    (p->p_p->ps_flags & PS_NOBTCFI) == 0) {
+		uint64_t msr = rdmsr(MSR_U_CET);
+		wrmsr(MSR_U_CET, msr | MSR_CET_ENDBR_EN | MSR_CET_NO_TRACK_EN);
+	}
+#endif
+}
+
+static inline void
+initialize_thread_xstate(struct proc *p)
+{
+	if (cpu_use_xsaves) {
+		xrstors(fpu_cleandata, xsave_mask);
+		maybe_enable_user_cet(p);
+	} else {
+		/* Reset FPU state in PCB */
+		memcpy(&p->p_addr->u_pcb.pcb_savefpu, fpu_cleandata,
+		    fpu_save_len);
+
+		if (curcpu()->ci_pflags & CPUPF_USERXSTATE) {
+			/* state in CPU is obsolete; reset it */
+			fpureset();
+		}
+	}
+
+	/* The reset state _is_ the userspace state for this thread now */
+	curcpu()->ci_pflags |= CPUPF_USERXSTATE;
+}
+
+/*
+ * Copy out the FPU state, massaging it to be usable from userspace
+ * and acceptable to xrstor_user()
+ */
+static inline int
+copyoutfpu(struct savefpu *sfp, char *sp, size_t len)
+{
+	uint64_t bvs[2];
+
+	if (copyout(sfp, sp, len))
+		return 1;
+	if (len > offsetof(struct savefpu, fp_xstate.xstate_bv)) {
+		sp  += offsetof(struct savefpu, fp_xstate.xstate_bv);
+		len -= offsetof(struct savefpu, fp_xstate.xstate_bv);
+		bvs[0] = sfp->fp_xstate.xstate_bv & XFEATURE_XCR0_MASK;
+		bvs[1] = sfp->fp_xstate.xstate_xcomp_bv &
+		    (XFEATURE_XCR0_MASK | XFEATURE_COMPRESSED);
+		if (copyout(bvs, sp, min(len, sizeof bvs)))
+			return 1;
+	}
+	return 0;
+}
+
 /*
  * Send an interrupt to process.
  *
@@ -613,23 +670,22 @@ sendsig(sig_t catcher, int sig, sigset_t mask, const siginfo_t *ksip,
 	else
 		sp = tf->tf_rsp - 128;
 
-	sp &= ~15ULL;	/* just in case */
-	sss = (sizeof(ksc) + 15) & ~15;
+	sp -= fpu_save_len;
+	if (cpu_use_xsaves)
+		sp &= ~63ULL;	/* just in case */
+	else
+		sp &= ~15ULL;	/* just in case */
 
 	/* Save FPU state to PCB if necessary, then copy it out */
-	if (curcpu()->ci_pflags & CPUPF_USERXSTATE) {
-		curcpu()->ci_pflags &= ~CPUPF_USERXSTATE;
-		fpusavereset(&p->p_addr->u_pcb.pcb_savefpu);
-	}
-	sp -= fpu_save_len;
-	ksc.sc_fpstate = (struct fxsave64 *)sp;
-	if (copyout(sfp, (void *)sp, fpu_save_len))
+	if (curcpu()->ci_pflags & CPUPF_USERXSTATE)
+		fpusave(&p->p_addr->u_pcb.pcb_savefpu);
+	if (copyoutfpu(sfp, (void *)sp, fpu_save_len))
 		return 1;
 
-	/* Now reset the FPU state in PCB */
-	memcpy(&p->p_addr->u_pcb.pcb_savefpu,
-	    &proc0.p_addr->u_pcb.pcb_savefpu, fpu_save_len);
+	initialize_thread_xstate(p);
 
+	ksc.sc_fpstate = (struct fxsave64 *)sp;
+	sss = (sizeof(ksc) + 15) & ~15;
 	sip = 0;
 	if (info) {
 		sip = sp - ((sizeof(*ksip) + 15) & ~15);
@@ -658,9 +714,6 @@ sendsig(sig_t catcher, int sig, sigset_t mask, const siginfo_t *ksip,
 	tf->tf_rsp = scp;
 	tf->tf_ss = GSEL(GUDATA_SEL, SEL_UPL);
 
-	/* The reset state _is_ the userspace state for this thread now */
-	curcpu()->ci_pflags |= CPUPF_USERXSTATE;
-
 	return 0;
 }
 
@@ -682,6 +735,7 @@ sys_sigreturn(struct proc *p, void *v, register_t *retval)
 	} */ *uap = v;
 	struct sigcontext ksc, *scp = SCARG(uap, sigcntxp);
 	struct trapframe *tf = p->p_md.md_regs;
+	struct savefpu *sfp = &p->p_addr->u_pcb.pcb_savefpu;
 	int error;
 
 	if (PROC_PC(p) != p->p_p->ps_sigcoderet) {
@@ -706,7 +760,7 @@ sys_sigreturn(struct proc *p, void *v, register_t *retval)
 	    !USERMODE(ksc.sc_cs, ksc.sc_eflags))
 		return (EINVAL);
 
-	/* Current state is obsolete; toss it and force a reload */
+	/* Current FPU state is obsolete; toss it and force a reload */
 	if (curcpu()->ci_pflags & CPUPF_USERXSTATE) {
 		curcpu()->ci_pflags &= ~CPUPF_USERXSTATE;
 		fpureset();
@@ -714,15 +768,17 @@ sys_sigreturn(struct proc *p, void *v, register_t *retval)
 
 	/* Copy in the FPU state to restore */
 	if (__predict_true(ksc.sc_fpstate != NULL)) {
-		struct fxsave64 *fx = &p->p_addr->u_pcb.pcb_savefpu.fp_fxsave;
-
-		if ((error = copyin(ksc.sc_fpstate, fx, fpu_save_len)))
-			return (error);
-		fx->fx_mxcsr &= fpu_mxcsr_mask;
+		if ((error = copyin(ksc.sc_fpstate, sfp, fpu_save_len)))
+			return error;
+		if (xrstor_user(sfp, xsave_mask)) {
+			memcpy(sfp, fpu_cleandata, fpu_save_len);
+			return EINVAL;
+		}
+		maybe_enable_user_cet(p);
+		curcpu()->ci_pflags |= CPUPF_USERXSTATE;
 	} else {
 		/* shouldn't happen, but handle it */
-		memcpy(&p->p_addr->u_pcb.pcb_savefpu,
-		    &proc0.p_addr->u_pcb.pcb_savefpu, fpu_save_len);
+		initialize_thread_xstate(p);
 	}
 
 	tf->tf_rdi = ksc.sc_rdi;
@@ -1146,17 +1202,7 @@ setregs(struct proc *p, struct exec_package *pack, u_long stack,
 {
 	struct trapframe *tf;
 
-	/* Reset FPU state in PCB */
-	memcpy(&p->p_addr->u_pcb.pcb_savefpu,
-	    &proc0.p_addr->u_pcb.pcb_savefpu, fpu_save_len);
-
-	if (curcpu()->ci_pflags & CPUPF_USERXSTATE) {
-		/* state in CPU is obsolete; reset it */
-		fpureset();
-	} else {
-		/* the reset state _is_ the userspace state now */
-		curcpu()->ci_pflags |= CPUPF_USERXSTATE;
-	}
+	initialize_thread_xstate(p);
 
 	/* To reset all registers we have to return via iretq */
 	p->p_md.md_flags |= MDP_IRET;

sys/arch/amd64/amd64/vmm_machdep.c

@@ -1,4 +1,4 @@
-/* $OpenBSD: vmm_machdep.c,v 1.3 2023/04/26 15:40:51 mlarkin Exp $ */
+/* $OpenBSD: vmm_machdep.c,v 1.4 2023/07/10 03:32:10 guenther Exp $ */
 /*
  * Copyright (c) 2014 Mike Larkin <mlarkin@openbsd.org>
  *
@@ -3733,13 +3733,8 @@ vmm_fpurestore(struct vcpu *vcpu)
 		fpusavereset(&curproc->p_addr->u_pcb.pcb_savefpu);
 	}
 
-	if (vcpu->vc_fpuinited) {
-		if (xrstor_user(&vcpu->vc_g_fpu, xsave_mask)) {
-			DPRINTF("%s: guest attempted to set invalid %s\n",
-			    __func__, "xsave/xrstor state");
-			return EINVAL;
-		}
-	}
+	if (vcpu->vc_fpuinited)
+		xrstor_kern(&vcpu->vc_g_fpu, xsave_mask);
 
 	if (xsave_mask) {
 		/* Restore guest %xcr0 */
@@ -3769,7 +3764,7 @@ vmm_fpusave(struct vcpu *vcpu)
 		vcpu->vc_gueststate.vg_xcr0 = xgetbv(0);
 
 		/* Restore host %xcr0 */
-		xsetbv(0, xsave_mask);
+		xsetbv(0, xsave_mask & XFEATURE_XCR0_MASK);
 	}
 
 	/*

sys/arch/amd64/conf/RAMDISK

@@ -1,4 +1,4 @@
-#	$OpenBSD: RAMDISK,v 1.85 2021/12/26 13:55:36 kettenis Exp $
+#	$OpenBSD: RAMDISK,v 1.86 2023/07/20 02:26:24 yasuoka Exp $
 
 machine		amd64
 maxusers	4
@@ -77,7 +77,7 @@ pckbd*		at pckbc?	# PC keyboard
 wskbd*		at pckbd? mux 1
 vga0		at isa?
 vga*		at pci?
-wsdisplay*	at vga?
+wsdisplay0	at vga? console 1
 
 com0		at isa? port 0x3f8 irq 4	# standard PC serial ports
 com1		at isa? port 0x2f8 irq 3

sys/arch/amd64/conf/RAMDISK_CD

@@ -1,4 +1,4 @@
-#	$OpenBSD: RAMDISK_CD,v 1.201 2023/04/02 03:40:54 kevlo Exp $
+#	$OpenBSD: RAMDISK_CD,v 1.202 2023/07/20 02:26:24 yasuoka Exp $
 
 machine		amd64
 maxusers	4
@@ -152,7 +152,7 @@ pckbd*		at pckbc?		# PC keyboard
 wskbd*		at pckbd? mux 1
 vga0		at isa?
 vga*		at pci?
-wsdisplay*	at vga?
+wsdisplay0	at vga? console 1
 
 efifb0		at mainbus?		# EFI Framebuffer
 wsdisplay0	at efifb? console 1

sys/arch/amd64/include/codepatch.h

@@ -1,4 +1,4 @@
-/*      $OpenBSD: codepatch.h,v 1.14 2020/03/11 07:27:08 guenther Exp $    */
+/*      $OpenBSD: codepatch.h,v 1.15 2023/07/10 03:32:10 guenther Exp $    */
 /*
  * Copyright (c) 2014-2015 Stefan Fritsch <sf@sfritsch.de>
  *
@@ -65,6 +65,7 @@ void codepatch_disable(void);
 #define CPTAG_MDS_VMM		10
 #define CPTAG_FENCE_SWAPGS_MIS_TAKEN	11
 #define CPTAG_FENCE_NO_SAFE_SMAP	12
+#define CPTAG_XRSTORS			13
 
 /*
  * stac/clac SMAP instructions have lfence like semantics.  Let's

sys/arch/amd64/include/fpu.h

@@ -1,4 +1,4 @@
-/*	$OpenBSD: fpu.h,v 1.18 2023/05/22 00:39:57 guenther Exp $	*/
+/*	$OpenBSD: fpu.h,v 1.19 2023/07/10 03:32:10 guenther Exp $	*/
 /*	$NetBSD: fpu.h,v 1.1 2003/04/26 18:39:40 fvdl Exp $	*/
 
 #ifndef	_MACHINE_FPU_H_
@@ -40,6 +40,7 @@ struct savefpu {
 	struct fxsave64 fp_fxsave;	/* see above */
 	struct xstate_hdr fp_xstate;
 	u_int64_t fp_ymm[16][2];
+	u_int64_t fp_cet_u[2];
 };
 
 /*
@@ -60,6 +61,7 @@ struct cpu_info;
 extern size_t	fpu_save_len;
 extern uint32_t	fpu_mxcsr_mask;
 extern uint64_t	xsave_mask;
+extern int cpu_use_xsaves;
 
 void fpuinit(struct cpu_info *);
 int fputrap(int _type);
@@ -68,9 +70,13 @@ void fpusavereset(struct savefpu *);
 void fpu_kernel_enter(void);
 void fpu_kernel_exit(void);
 
+/* pointer to fxsave/xsave/xsaves data with everything reset */
+#define	fpu_cleandata	(&proc0.p_addr->u_pcb.pcb_savefpu)
+
 int	xrstor_user(struct savefpu *_addr, uint64_t _mask);
+void	xrstor_kern(struct savefpu *_addr, uint64_t _mask);
 #define	fpureset() \
-	xrstor_user(&proc0.p_addr->u_pcb.pcb_savefpu, xsave_mask)
+	xrstor_kern(fpu_cleandata, xsave_mask)
 int	xsetbv_user(uint32_t _reg, uint64_t _mask);
 
 #define fninit()		__asm("fninit")
@@ -87,9 +93,17 @@ xsave(struct savefpu *addr, uint64_t mask)
 
 	lo = mask;
 	hi = mask >> 32;
-	/* should be xsave64, but where we use this it doesn't matter */
-	__asm volatile("xsave %0" : "=m" (*addr) : "a" (lo), "d" (hi) :
-	    "memory");
+	__asm volatile("xsave64 %0" : "+m" (*addr) : "a" (lo), "d" (hi));
+}
+
+static inline void
+xrstors(const struct savefpu *addr, uint64_t mask)
+{
+	uint32_t lo, hi;
+
+	lo = mask;
+	hi = mask >> 32;
+	__asm volatile("xrstors64 %0" : : "m" (*addr), "a" (lo), "d" (hi));
 }
 
 #endif

sys/arch/amd64/include/specialreg.h

@@ -1,4 +1,4 @@
-/*	$OpenBSD: specialreg.h,v 1.102 2023/04/22 18:27:28 guenther Exp $	*/
+/*	$OpenBSD: specialreg.h,v 1.103 2023/07/10 03:32:10 guenther Exp $	*/
 /*	$NetBSD: specialreg.h,v 1.1 2003/04/26 18:39:48 fvdl Exp $	*/
 /*	$NetBSD: x86/specialreg.h,v 1.2 2003/04/25 21:54:30 fvdl Exp $	*/
 
@@ -118,6 +118,9 @@
 #define	XFEATURE_TILEDATA	0x00040000	/* AMX state */
 #define	XFEATURE_AMX		(XFEATURE_TILEDATA | XFEATURE_TILEDATA)
 
+/* valid only in xcomp_bv field: */
+#define XFEATURE_COMPRESSED	(1ULL << 63)	/* compressed format */
+
 /* which bits are for XCR0 and which for the XSS MSR? */
 #define XFEATURE_XCR0_MASK \
 	(XFEATURE_X87 | XFEATURE_SSE | XFEATURE_AVX | XFEATURE_MPX | \
@@ -525,6 +528,7 @@
 #define MSR_MC3_MISC		0x413
 #define MSR_U_CET		0x6a0
 #define MSR_CET_ENDBR_EN		(1 << 2)
+#define MSR_CET_NO_TRACK_EN		(1 << 4)
 #define MSR_S_CET		0x6a2
 #define MSR_PKRS		0x6e1
 #define MSR_XSS			0xda0

sys/arch/arm64/arm64/cpu.c

@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpu.c,v 1.95 2023/06/15 22:18:07 cheloha Exp $	*/
+/*	$OpenBSD: cpu.c,v 1.97 2023/07/16 16:13:46 kettenis Exp $	*/
 
 /*
  * Copyright (c) 2016 Dale Rahn <drahn@dalerahn.com>
@@ -1010,6 +1010,8 @@ void cpu_boot_secondary(struct cpu_info *ci);
 void cpu_hatch_secondary(void);
 void cpu_hatch_secondary_spin(void);
 
+void cpu_suspend_cycle(void);
+
 void
 cpu_boot_secondary_processors(void)
 {
@@ -1224,7 +1226,7 @@ cpu_halt(void)
 				ci->ci_psci_suspend_param = 0;
 		} else
 #endif
-			__asm volatile("wfi");
+			cpu_suspend_cycle();
 		count++;
 	}
 
@@ -1236,8 +1238,6 @@ cpu_halt(void)
 	/* Unmask clock interrupts. */
 	WRITE_SPECIALREG(cntv_ctl_el0,
 	    READ_SPECIALREG(cntv_ctl_el0) & ~CNTV_CTL_IMASK);
-
-	printf("%s: %d wakeup events\n", ci->ci_dev->dv_xname, count);
 }
 
 void
@@ -1266,9 +1266,16 @@ cpu_unidle(struct cpu_info *ci)
 
 void cpu_hatch_primary(void);
 
+void (*cpu_suspend_cycle_fcn)(void) = cpu_wfi;
 label_t cpu_suspend_jmpbuf;
 int cpu_suspended;
 
+void
+cpu_suspend_cycle(void)
+{
+	cpu_suspend_cycle_fcn();
+}
+
 void
 cpu_init_primary(void)
 {
@@ -1342,7 +1349,7 @@ cpu_suspend_primary(void)
 				ci->ci_psci_suspend_param = 0;
 		} else
 #endif
-			__asm volatile("wfi");
+			cpu_suspend_cycle();
 		count++;
 	}
 
@@ -1353,8 +1360,6 @@ resume:
 	WRITE_SPECIALREG(cntv_ctl_el0,
 	    READ_SPECIALREG(cntv_ctl_el0) & ~CNTV_CTL_IMASK);
 
-	printf("%s: %d wakeup events\n", ci->ci_dev->dv_xname, count);
-
 	return 0;
 }
 

sys/arch/arm64/arm64/cpufunc_asm.S

@@ -1,4 +1,4 @@
-/* $OpenBSD: cpufunc_asm.S,v 1.7 2020/11/20 21:48:33 patrick Exp $ */
+/* $OpenBSD: cpufunc_asm.S,v 1.8 2023/07/13 08:33:36 kettenis Exp $ */
 /*-
  * Copyright (c) 2014 Robin Randhawa
  * Copyright (c) 2015 The FreeBSD Foundation
@@ -185,3 +185,52 @@ ENTRY(cpu_icache_sync_range)
 	RETGUARD_CHECK(cpu_icache_sync_range, x15)
 	ret
 END(cpu_icache_sync_range)
+
+ENTRY(cpu_wfi)
+	RETGUARD_SETUP(cpu_wfi, x15)
+	dsb	sy
+	wfi
+	RETGUARD_CHECK(cpu_wfi, x15)
+	ret
+END(cpu_wfi)
+
+ENTRY(aplcpu_deep_wfi)
+	RETGUARD_SETUP(aplcpu_deep_wfi, x15)
+
+	stp	x30, x15, [sp, #-16]!
+	stp	x28, x29, [sp, #-16]!
+	stp	x26, x27, [sp, #-16]!
+	stp	x24, x25, [sp, #-16]!
+	stp	x22, x23, [sp, #-16]!
+	stp	x20, x21, [sp, #-16]!
+	stp	x18, x19, [sp, #-16]!
+
+	mrs	x0, daif
+	str	x0, [sp, #-16]!
+	msr	daifset, #3
+
+	mrs	x0, s3_5_c15_c5_0
+	orr	x0, x0, #(3 << 24)
+	msr	s3_5_c15_c5_0, x0
+
+	dsb	sy
+	wfi
+
+	mrs	x0, s3_5_c15_c5_0
+	bic	x0, x0, #(1 << 24)
+	msr	s3_5_c15_c5_0, x0
+
+	ldr	x0, [sp], #16
+	msr	daif, x0
+
+	ldp	x18, x19, [sp], #16
+	ldp	x20, x21, [sp], #16
+	ldp	x22, x23, [sp], #16
+	ldp	x24, x25, [sp], #16
+	ldp	x26, x27, [sp], #16
+	ldp	x28, x29, [sp], #16
+	ldp	x30, x15, [sp], #16
+
+	RETGUARD_CHECK(aplcpu_deep_wfi, x15)
+	ret
+END(aplcpu_deep_wfi)

sys/arch/arm64/arm64/machdep.c

@@ -1,4 +1,4 @@
-/* $OpenBSD: machdep.c,v 1.82 2023/06/10 19:30:48 kettenis Exp $ */
+/* $OpenBSD: machdep.c,v 1.83 2023/07/13 08:33:36 kettenis Exp $ */
 /*
  * Copyright (c) 2014 Patrick Wildt <patrick@blueri.se>
  * Copyright (c) 2021 Mark Kettenis <kettenis@openbsd.org>
@@ -211,12 +211,13 @@ cpu_idle_enter(void)
 {
 }
 
+void (*cpu_idle_cycle_fcn)(void) = cpu_wfi;
+
 void
 cpu_idle_cycle(void)
 {
 	enable_irq_daif();
-	__asm volatile("dsb sy" ::: "memory");
-	__asm volatile("wfi");
+	cpu_idle_cycle_fcn();
 }
 
 void

sys/arch/arm64/conf/GENERIC

@@ -1,4 +1,4 @@
-# $OpenBSD: GENERIC,v 1.275 2023/07/01 16:34:29 drahn Exp $
+# $OpenBSD: GENERIC,v 1.276 2023/07/19 20:27:20 kettenis Exp $
 #
 # GENERIC machine description file
 #
@@ -177,7 +177,7 @@ nvme*		at aplns?
 aplpcie*	at fdt?
 pci*		at aplpcie?
 aplpinctrl*	at fdt? early 1
-aplpmgr*	at fdt? early 1
+aplpmgr*	at fdt? early 2
 aplpwm*		at fdt?
 aplrtk*		at fdt?
 aplsart*	at fdt?

sys/arch/arm64/conf/RAMDISK

@@ -1,4 +1,4 @@
-# $OpenBSD: RAMDISK,v 1.207 2023/06/27 22:38:46 patrick Exp $
+# $OpenBSD: RAMDISK,v 1.208 2023/07/19 20:27:20 kettenis Exp $
 
 machine		arm64
 maxusers	4
@@ -128,7 +128,7 @@ nvme*		at aplns?
 aplpcie*	at fdt?
 pci*		at aplpcie?
 aplpinctrl*	at fdt? early 1
-aplpmgr*	at fdt? early 1
+aplpmgr*	at fdt? early 2
 aplrtk*		at fdt?
 aplsart*	at fdt?
 aplsmc*		at fdt?

sys/arch/arm64/dev/aplcpu.c

@@ -1,4 +1,4 @@
-/*	$OpenBSD: aplcpu.c,v 1.7 2023/05/09 10:13:23 kettenis Exp $	*/
+/*	$OpenBSD: aplcpu.c,v 1.8 2023/07/13 08:33:36 kettenis Exp $	*/
 /*
  * Copyright (c) 2022 Mark Kettenis <kettenis@openbsd.org>
  *
@@ -42,6 +42,8 @@
 #define DVFS_T8112_STATUS_CUR_PS_MASK	(0x1f << 5)
 #define DVFS_T8112_STATUS_CUR_PS_SHIFT	5
 
+#define APLCPU_DEEP_WFI_LATENCY		10 /* microseconds */
+
 struct opp {
 	uint64_t opp_hz;
 	uint32_t opp_level;
@@ -97,6 +99,8 @@ uint32_t aplcpu_opp_level(struct aplcpu_softc *, int);
 int	aplcpu_clockspeed(int *);
 void	aplcpu_setperf(int level);
 void	aplcpu_refresh_sensors(void *);
+void	aplcpu_idle_cycle();
+void	aplcpu_deep_wfi(void);
 
 int
 aplcpu_match(struct device *parent, void *match, void *aux)
@@ -171,6 +175,8 @@ aplcpu_attach(struct device *parent, struct device *self, void *aux)
 	sensordev_install(&sc->sc_sensordev);
 	sensor_task_register(sc, aplcpu_refresh_sensors, 1);
 
+	cpu_idle_cycle_fcn = aplcpu_idle_cycle;
+	cpu_suspend_cycle_fcn = aplcpu_deep_wfi;
 	cpu_cpuspeed = aplcpu_clockspeed;
 	cpu_setperf = aplcpu_setperf;
 	return;
@@ -223,11 +229,8 @@ aplcpu_opp_init(struct aplcpu_softc *sc, int node)
 		return;
 
 	count = 0;
-	for (child = OF_child(node); child != 0; child = OF_peer(child)) {
-		if (OF_getproplen(child, "turbo-mode") == 0)
-			continue;
+	for (child = OF_child(node); child != 0; child = OF_peer(child))
 		count++;
-	}
 	if (count == 0)
 		return;
 
@@ -239,8 +242,6 @@ aplcpu_opp_init(struct aplcpu_softc *sc, int node)
 
 	count = 0;
 	for (child = OF_child(node); child != 0; child = OF_peer(child)) {
-		if (OF_getproplen(child, "turbo-mode") == 0)
-			continue;
 		opp_hz = OF_getpropint64(child, "opp-hz", 0);
 		opp_level = OF_getpropint(child, "opp-level", 0);
 
@@ -430,3 +431,27 @@ aplcpu_refresh_sensors(void *arg)
 		}
 	}
 }
+
+void
+aplcpu_idle_cycle(void)
+{
+	struct cpu_info *ci = curcpu();
+	struct timeval start, stop;
+	u_long itime;
+
+	microuptime(&start);
+
+	if (ci->ci_prev_sleep > 3 * APLCPU_DEEP_WFI_LATENCY)
+		aplcpu_deep_wfi();
+	else
+		cpu_wfi();
+
+	microuptime(&stop);
+	timersub(&stop, &start, &stop);
+	itime = stop.tv_sec * 1000000 + stop.tv_usec;
+
+	ci->ci_last_itime = itime;
+	itime >>= 1;
+	ci->ci_prev_sleep = (ci->ci_prev_sleep + (ci->ci_prev_sleep >> 1)
+	    + itime) >> 1;
+}

sys/arch/arm64/dev/aplpmgr.c

@@ -1,4 +1,4 @@
-/*	$OpenBSD: aplpmgr.c,v 1.3 2022/11/10 11:44:06 kettenis Exp $	*/
+/*	$OpenBSD: aplpmgr.c,v 1.5 2023/07/20 20:40:44 kettenis Exp $	*/
 /*
  * Copyright (c) 2021 Mark Kettenis <kettenis@openbsd.org>
  *
@@ -66,7 +66,6 @@ struct aplpmgr_softc {
 
 int	aplpmgr_match(struct device *, void *, void *);
 void	aplpmgr_attach(struct device *, struct device *, void *);
-int	aplpmgr_activate(struct device *, int act);
 
 const struct cfattach aplpmgr_ca = {
 	sizeof (struct aplpmgr_softc), aplpmgr_match, aplpmgr_attach

sys/arch/arm64/dev/aplsmc.c

@@ -1,4 +1,4 @@
-/*	$OpenBSD: aplsmc.c,v 1.24 2023/07/08 14:44:43 tobhe Exp $	*/
+/*	$OpenBSD: aplsmc.c,v 1.25 2023/07/16 16:11:11 kettenis Exp $	*/
 /*
  * Copyright (c) 2021 Mark Kettenis <kettenis@openbsd.org>
  *
@@ -138,6 +138,7 @@ struct aplsmc_softc {
 	struct ksensor		sc_sensors[APLSMC_MAX_SENSORS];
 	int			sc_nsensors;
 	struct ksensordev	sc_sensordev;
+	uint32_t		sc_suspend_pstr;
 };
 
 #define CH0I_DISCHARGE		(1 << 0)
@@ -175,9 +176,11 @@ struct aplsmc_sensor aplsmc_sensors[] = {
 
 int	aplsmc_match(struct device *, void *, void *);
 void	aplsmc_attach(struct device *, struct device *, void *);
+int	aplsmc_activate(struct device *, int);
 
 const struct cfattach aplsmc_ca = {
-	sizeof (struct aplsmc_softc), aplsmc_match, aplsmc_attach
+	sizeof (struct aplsmc_softc), aplsmc_match, aplsmc_attach,
+	NULL, aplsmc_activate
 };
 
 struct cfdriver aplsmc_cd = {
@@ -189,6 +192,7 @@ int	aplsmc_send_cmd(struct aplsmc_softc *, uint16_t, uint32_t, uint16_t);
 int	aplsmc_wait_cmd(struct aplsmc_softc *sc);
 int	aplsmc_read_key(struct aplsmc_softc *, uint32_t, void *, size_t);
 int	aplsmc_write_key(struct aplsmc_softc *, uint32_t, void *, size_t);
+int64_t aplsmc_convert_flt(uint32_t, int);
 void	aplsmc_refresh_sensors(void *);
 int	aplsmc_apminfo(struct apm_power_info *);
 void	aplsmc_set_pin(void *, uint32_t *, int);
@@ -357,7 +361,24 @@ aplsmc_attach(struct device *parent, struct device *self, void *aux)
 #ifdef SUSPEND
 	device_register_wakeup(&sc->sc_dev);
 #endif
+}
 
+int
+aplsmc_activate(struct device *self, int act)
+{
+#ifdef SUSPEND
+	struct aplsmc_softc *sc = (struct aplsmc_softc *)self;
+	int64_t value;
+
+	switch (act) {
+	case DVACT_WAKEUP:
+		value = aplsmc_convert_flt(sc->sc_suspend_pstr, 100);
+		printf("%s: system %lld.%02lld W\n", sc->sc_dev.dv_xname,
+		    value / 100, value % 100);
+	}
+#endif
+
+	return 0;
 }
 
 void
@@ -366,8 +387,12 @@ aplsmc_handle_notification(struct aplsmc_softc *sc, uint64_t data)
 	extern int allowpowerdown;
 #ifdef SUSPEND
 	extern int cpu_suspended;
+	uint32_t flt = 0;
 
 	if (cpu_suspended) {
+		aplsmc_read_key(sc, 'PSTR', &flt, sizeof(flt));
+		sc->sc_suspend_pstr = flt;
+
 		switch (SMC_EV_TYPE(data)) {
 		case SMC_EV_TYPE_BTN:
 			switch (SMC_EV_SUBTYPE(data)) {
@@ -542,6 +567,26 @@ aplsmc_write_key(struct aplsmc_softc *sc, uint32_t key, void *data, size_t len)
 
 #ifndef SMALL_KERNEL
 
+int64_t
+aplsmc_convert_flt(uint32_t flt, int scale)
+{
+	int64_t mant;
+	int sign, exp;
+
+	/*
+	 * Convert floating-point to integer, trying to keep as much
+	 * resolution as possible given the scaling factor.
+	 */
+	sign = (flt >> 31) ? -1 : 1;
+	exp = ((flt >> 23) & 0xff) - 127;
+	mant = (flt & 0x7fffff) | 0x800000;
+	mant *= scale;
+	if (exp < 23)
+		return sign * (mant >> (23 - exp));
+	else
+		return sign * (mant << (exp - 23));
+}
+
 void
 aplsmc_refresh_sensors(void *arg)
 {
@@ -570,26 +615,11 @@ aplsmc_refresh_sensors(void *arg)
 			value = (int64_t)ui16 * sensor->scale;
 		} else if (strcmp(sensor->key_type, "flt ") == 0) {
 			uint32_t flt;
-			int64_t mant;
-			int sign, exp;
 
 			error = aplsmc_read_key(sc, key, &flt, sizeof(flt));
 			if (sensor->flags & APLSMC_BE)
 				flt = betoh32(flt);
-
-			/*
-			 * Convert floating-point to integer, trying
-			 * to keep as much resolution as possible
-			 * given the scaling factor for this sensor.
-			 */
-			sign = (flt >> 31) ? -1 : 1;
-			exp = ((flt >> 23) & 0xff) - 127;
-			mant = (flt & 0x7fffff) | 0x800000;
-			mant *= sensor->scale;
-			if (exp < 23)
-				value = sign * (mant >> (23 - exp));
-			else
-				value = sign * (mant << (exp - 23));
+			value = aplsmc_convert_flt(flt, sensor->scale);
 		}
 
 		/* Apple reports temperatures in degC. */

sys/arch/arm64/dev/mainbus.c

@@ -1,4 +1,4 @@
-/* $OpenBSD: mainbus.c,v 1.25 2023/05/19 21:15:16 patrick Exp $ */
+/* $OpenBSD: mainbus.c,v 1.27 2023/07/19 21:52:55 kettenis Exp $ */
 /*
  * Copyright (c) 2016 Patrick Wildt <patrick@blueri.se>
  * Copyright (c) 2017 Mark Kettenis <kettenis@openbsd.org>
@@ -154,13 +154,11 @@ mainbus_attach(struct device *parent, struct device *self, void *aux)
 	mainbus_attach_apm(self);
 
 	/* Scan the whole tree. */
-	sc->sc_early = 1;
-	for (node = OF_child(sc->sc_node); node != 0; node = OF_peer(node))
-		mainbus_attach_node(self, node, NULL);
-
+	for (sc->sc_early = 2; sc->sc_early >= 0; sc->sc_early--) {
+		for (node = OF_child(sc->sc_node); node; node = OF_peer(node))
+			mainbus_attach_node(self, node, NULL);
+	}
 	sc->sc_early = 0;
-	for (node = OF_child(sc->sc_node); node != 0; node = OF_peer(node))
-		mainbus_attach_node(self, node, NULL);
 
 	mainbus_attach_framebuffer(self);
 

sys/arch/arm64/dev/simplebus.c

@@ -1,4 +1,4 @@
-/* $OpenBSD: simplebus.c,v 1.16 2022/11/06 12:01:52 patrick Exp $ */
+/* $OpenBSD: simplebus.c,v 1.17 2023/07/19 20:26:11 kettenis Exp $ */
 /*
  * Copyright (c) 2016 Patrick Wildt <patrick@blueri.se>
  *
@@ -140,13 +140,10 @@ simplebus_attach(struct device *parent, struct device *self, void *aux)
 	}
 
 	/* Scan the whole tree. */
-	sc->sc_early = 1;
-	for (node = OF_child(sc->sc_node); node; node = OF_peer(node))
-		simplebus_attach_node(self, node);
-
-	sc->sc_early = 0;
-	for (node = OF_child(sc->sc_node); node; node = OF_peer(node))
-		simplebus_attach_node(self, node);
+	for (sc->sc_early = 2; sc->sc_early >= 0; sc->sc_early--) {
+		for (node = OF_child(sc->sc_node); node; node = OF_peer(node))
+			simplebus_attach_node(self, node);
+	}
 }
 
 int

sys/arch/arm64/include/cpu.h

@@ -1,4 +1,4 @@
-/* $OpenBSD: cpu.h,v 1.36 2023/06/10 19:30:48 kettenis Exp $ */
+/* $OpenBSD: cpu.h,v 1.37 2023/07/13 08:33:36 kettenis Exp $ */
 /*
  * Copyright (c) 2016 Dale Rahn <drahn@dalerahn.com>
  *
@@ -154,6 +154,9 @@ struct cpu_info {
 	volatile int		ci_opp_max;
 	uint32_t		ci_cpu_supply;
 
+	u_long			ci_prev_sleep;
+	u_long			ci_last_itime;
+
 #ifdef MULTIPROCESSOR
 	struct srp_hazard	ci_srp_hazards[SRP_HAZARD_NUM];
 	volatile int		ci_flags;
@@ -344,6 +347,11 @@ void	cpu_startclock(void);
 int	cpu_suspend_primary(void);
 void	cpu_resume_secondary(struct cpu_info *);
 
+extern void (*cpu_idle_cycle_fcn)(void);
+extern void (*cpu_suspend_cycle_fcn)(void);
+
+void	cpu_wfi(void);
+
 void	delay (unsigned);
 #define	DELAY(x)	delay(x)
 

sys/arch/i386/conf/RAMDISK

@@ -1,4 +1,4 @@
-#	$OpenBSD: RAMDISK,v 1.201 2021/02/16 00:03:54 deraadt Exp $
+#	$OpenBSD: RAMDISK,v 1.202 2023/07/20 02:26:24 yasuoka Exp $
 
 machine		i386
 maxusers	4
@@ -84,8 +84,8 @@ wskbd*		at pckbd? mux 1
 vga0		at isa?
 vga*		at pci?
 pcdisplay0	at isa?			# CGA, MDA, EGA, HGA
-wsdisplay*	at vga?
-wsdisplay*	at pcdisplay?
+wsdisplay0	at vga? console 1
+wsdisplay0	at pcdisplay? console 1
 
 com0		at isa? port 0x3f8 irq 4	# standard PC serial ports
 com1		at isa? port 0x2f8 irq 3

sys/arch/i386/conf/RAMDISK_CD

@@ -1,4 +1,4 @@
-#	$OpenBSD: RAMDISK_CD,v 1.252 2022/06/26 20:05:06 sthen Exp $
+#	$OpenBSD: RAMDISK_CD,v 1.253 2023/07/20 02:26:24 yasuoka Exp $
 
 machine		i386
 maxusers	4
@@ -124,8 +124,8 @@ wskbd*		at pckbd? mux 1
 vga0		at isa?
 vga*		at pci?
 pcdisplay0	at isa?		# CGA, MDA, EGA, HGA
-wsdisplay*	at vga?
-wsdisplay*	at pcdisplay?
+wsdisplay0	at vga? console 1
+wsdisplay0	at pcdisplay? console 1
 
 com0		at isa? port 0x3f8 irq 4	# standard PC serial ports
 com1		at isa? port 0x2f8 irq 3

sys/arch/i386/i386/db_memrw.c

@@ -128,7 +128,7 @@ db_write_text(vaddr_t addr, size_t size, char *data)
 		 */
 		pmap_update_pg(pgva);
 		pmap_pte_setbits(addr, bits, PG_RW);
-		
+
 	} while (size != 0);
 }
 

sys/arch/i386/i386/dkcsum.c

@@ -171,7 +171,7 @@ dkcsumattach(void)
 #ifdef DEBUG
 			printf("dkcsum: %s has no matching BIOS drive\n",
 			    dv->dv_xname);
-#endif	
+#endif
 			continue;
 		}
 

sys/arch/i386/i386/esm.c

@@ -1033,7 +1033,7 @@ esm_cmd(struct esm_softc *sc, void *cmd, size_t cmdlen, void *resp,
 		/* Set host busy semaphore and clear doorbell */
 		ECTRLWR(sc, ESM2_TC_HOSTBUSY);
 		ECTRLWR(sc, ESM2_TC_EC2HDB);
-	
+
 		/* Read response data from port */
 		ECTRLWR(sc, ESM2_TC_CLR_RPTR);
 		for (i = 0; i < resplen; i++) {

sys/arch/i386/i386/est.c

@@ -1138,7 +1138,7 @@ est_init(struct cpu_info *ci, int vendor)
 			 * disable EST: - A lowest clock ratio of 0, which
 			 * seems to happen on all Pentium 4's that report EST.
 			 * - An equal highest and lowest clock ratio, which
-			 * happens on at least the Core 2 Duo X6800, maybe on 
+			 * happens on at least the Core 2 Duo X6800, maybe on
 			 * newer models too.
 			 */
 			return;

sys/arch/i386/i386/i686_mem.c

@@ -135,7 +135,7 @@ mem_range_match(struct mem_range_softc *sc, struct mem_range_desc *mrd)
 {
 	struct mem_range_desc	*cand;
 	int			 i;
-	
+
 	for (i = 0, cand = sc->mr_desc; i < sc->mr_ndesc; i++, cand++)
 		if ((cand->mr_base == mrd->mr_base) &&
 		    (cand->mr_len == mrd->mr_len))
@@ -159,7 +159,7 @@ mrfetch(struct mem_range_softc *sc)
 
 	/* We should never be fetching MTRRs from an AP */
 	KASSERT(CPU_IS_PRIMARY(curcpu()));
-	
+
 	/* Get fixed-range MTRRs, if the CPU supports them */
 	if (sc->mr_cap & MR_FIXMTRR) {
 		msr = MSR_MTRRfix64K_00000;
@@ -242,9 +242,9 @@ int
 mtrrtype(u_int64_t flags)
 {
 	int i;
-	
+
 	flags &= MDF_ATTRMASK;
-	
+
 	for (i = 0; i < nitems(mtrrtomrt); i++) {
 		if (mtrrtomrt[i] == MDF_UNKNOWN)
 			continue;
@@ -295,9 +295,9 @@ mrstoreone(struct mem_range_softc *sc)
 	u_int64_t		 msrv;
 	int			 i, j, msr;
 	u_int			 cr4save;
-	
+
 	mrd = sc->mr_desc;
-	
+
 	cr4save = rcr4();	/* save cr4 */
 	if (cr4save & CR4_PGE)
 		lcr4(cr4save & ~CR4_PGE);
@@ -306,7 +306,7 @@ mrstoreone(struct mem_range_softc *sc)
 	wbinvd();
 	lcr0((rcr0() & ~CR0_NW) | CR0_CD);
 	wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) & ~MTRRdefType_ENABLE);
-	
+
 	/* Set fixed-range MTRRs */
 	if (sc->mr_cap & MR_FIXMTRR) {
 		msr = MSR_MTRRfix64K_00000;
@@ -340,7 +340,7 @@ mrstoreone(struct mem_range_softc *sc)
 			mrd += 8;
 		}
 	}
-	
+
 	/* Set remainder which must be variable MTRRs */
 	msr = MSR_MTRRvarBase;
 	for (; (mrd - sc->mr_desc) < sc->mr_ndesc; msr += 2, mrd++) {
@@ -350,8 +350,8 @@ mrstoreone(struct mem_range_softc *sc)
 		} else
 			msrv = 0;
 
-		wrmsr(msr, msrv);	
-		
+		wrmsr(msr, msrv);
+
 		/* mask/active register */
 		if (mrd->mr_flags & MDF_ACTIVE) {
 			msrv = 0x800 | (~(mrd->mr_len - 1) & mtrrmask);
@@ -375,7 +375,7 @@ mtrrfixsearch(struct mem_range_softc *sc, u_int64_t addr)
 {
 	struct mem_range_desc *mrd;
 	int			i;
-	
+
 	for (i = 0, mrd = sc->mr_desc; i < (MTRR_N64K + MTRR_N16K + MTRR_N4K); i++, mrd++)
 		if ((addr >= mrd->mr_base) && (addr < (mrd->mr_base + mrd->mr_len)))
 			return(mrd);
@@ -399,7 +399,7 @@ mrsetlow(struct mem_range_softc *sc, struct mem_range_desc *mrd, int *arg)
 	if (((first_md = mtrrfixsearch(sc, mrd->mr_base)) == NULL) ||
 	    ((last_md = mtrrfixsearch(sc, mrd->mr_base + mrd->mr_len - 1)) == NULL))
 		return(EINVAL);
-	
+
 	/* check we aren't doing something risky */
 	if (!(mrd->mr_flags & MDF_FORCE))
 		for (curr_md = first_md; curr_md <= last_md; curr_md++) {
@@ -412,7 +412,7 @@ mrsetlow(struct mem_range_softc *sc, struct mem_range_desc *mrd, int *arg)
 		curr_md->mr_flags = mrcopyflags(curr_md->mr_flags & ~MDF_FIRMWARE, mrd->mr_flags);
 		bcopy(mrd->mr_owner, curr_md->mr_owner, sizeof(mrd->mr_owner));
 	}
-	
+
 	return(0);
 }
 
@@ -464,7 +464,7 @@ mrsetvariable(struct mem_range_softc *sc, struct mem_range_desc *mrd, int *arg)
 	/* got somewhere to put it? */
 	if (free_md == NULL)
 		return(ENOSPC);
-	
+
 	/* Set up new descriptor */
 	free_md->mr_base = mrd->mr_base;
 	free_md->mr_len = mrd->mr_len;
@@ -488,7 +488,7 @@ mrset(struct mem_range_softc *sc, struct mem_range_desc *mrd, int *arg)
 		if (!mrvalid(mrd->mr_base, mrd->mr_len) ||
 		    mtrrtype(mrd->mr_flags) == -1)
 			return(EINVAL);
-		
+
 		/* are the "low memory" conditions applicable? */
 		if ((sc->mr_cap & MR_FIXMTRR) &&
 		    ((mrd->mr_base + mrd->mr_len) <= FIXTOP)) {
@@ -500,7 +500,7 @@ mrset(struct mem_range_softc *sc, struct mem_range_desc *mrd, int *arg)
 				return(error);
 		}
 		break;
-		
+
 	case MEMRANGE_SET_REMOVE:
 		if ((targ = mem_range_match(sc, mrd)) == NULL)
 			return(ENOENT);
@@ -509,11 +509,11 @@ mrset(struct mem_range_softc *sc, struct mem_range_desc *mrd, int *arg)
 		targ->mr_flags &= ~MDF_ACTIVE;
 		targ->mr_owner[0] = 0;
 		break;
-		
+
 	default:
 		return(EOPNOTSUPP);
 	}
-	
+
 	/* update the hardware */
 	mrstore(sc);
 	return(0);
@@ -533,7 +533,7 @@ mrinit(struct mem_range_softc *sc)
 
 	mtrrcap = rdmsr(MSR_MTRRcap);
 	mtrrdef = rdmsr(MSR_MTRRdefType);
-	
+
 	/* For now, bail out if MTRRs are not enabled */
 	if (!(mtrrdef & MTRRdefType_ENABLE)) {
 		printf("mtrr: CPU supports MTRRs but not enabled by BIOS\n");
@@ -541,9 +541,9 @@ mrinit(struct mem_range_softc *sc)
 	}
 	nmdesc = mtrrcap & 0xff;
 	printf("mtrr: Pentium Pro MTRR support, %d var ranges", nmdesc);
-	
+
 	/* If fixed MTRRs supported and enabled */
-	if ((mtrrcap & MTRRcap_FIXED) && 
+	if ((mtrrcap & MTRRcap_FIXED) &&
 	    (mtrrdef & MTRRdefType_FIXED_ENABLE)) {
 		sc->mr_cap = MR_FIXMTRR;
 		nmdesc += MTRR_N64K + MTRR_N16K + MTRR_N4K;
@@ -551,13 +551,13 @@ mrinit(struct mem_range_softc *sc)
 	}
 
 	printf("\n");
-	
+
 	sc->mr_desc = mallocarray(nmdesc, sizeof(struct mem_range_desc),
 	     M_MEMDESC, M_WAITOK|M_ZERO);
 	sc->mr_ndesc = nmdesc;
-	
+
 	mrd = sc->mr_desc;
-	
+
 	/* Populate the fixed MTRR entries' base/length */
 	if (sc->mr_cap & MR_FIXMTRR) {
 		for (i = 0; i < MTRR_N64K; i++, mrd++) {
@@ -578,7 +578,7 @@ mrinit(struct mem_range_softc *sc)
 			mrd->mr_flags = MDF_FIXBASE | MDF_FIXLEN | MDF_FIXACTIVE;
 		}
 	}
-	
+
 	/*
 	 * Fetch maximum physical address size supported by the
 	 * processor as supported by CPUID leaf function 0x80000008.

sys/arch/i386/i386/ioapic.c

@@ -137,7 +137,7 @@ static __inline u_int32_t
 ioapic_read_ul(struct ioapic_softc *sc,int regid)
 {
 	u_int32_t val;
-	
+
 	*(sc->sc_reg) = regid;
 	val = *sc->sc_data;
 
@@ -493,7 +493,7 @@ apic_vectorset(struct ioapic_softc *sc, int pin, int minlevel, int maxlevel)
 {
 	struct ioapic_pin *pp = &sc->sc_pins[pin];
 	int nvector, ovector = pp->ip_vector;
-	
+
 	if (maxlevel == 0) {
 		/* no vector needed. */
 		pp->ip_minlevel = 0xff; /* XXX magic */
@@ -593,7 +593,7 @@ ioapic_enable(void)
 		for (p = 0; p < sc->sc_apic_sz; p++) {
 			maxlevel = 0;	 /* magic */
 			minlevel = 0xff; /* magic */
-				
+
 			for (q = sc->sc_pins[p].ip_handler; q != NULL;
 			     q = q->ih_next) {
 				if (q->ih_level > maxlevel)

sys/arch/i386/i386/ipifuncs.c

@@ -190,7 +190,7 @@ i386_broadcast_ipi(int ipimask)
 	if (!count)
 		return;
 
-	i386_ipi(LAPIC_IPI_VECTOR, LAPIC_DEST_ALLEXCL, LAPIC_DLMODE_FIXED); 
+	i386_ipi(LAPIC_IPI_VECTOR, LAPIC_DEST_ALLEXCL, LAPIC_DLMODE_FIXED);
 }
 
 void

sys/arch/i386/i386/k6_mem.c

@@ -108,7 +108,7 @@ k6_mrinit(struct mem_range_softc *sc)
 	reg = rdmsr(UWCCR);
 	for (d = 0; d < sc->mr_ndesc; d++) {
 		u_int32_t one = (reg & (0xffffffff << (32 * d))) >> (32 * d);
-		
+
 		k6_reg_get(one, addr, mask, wc, uc);
 		sc->mr_desc[d].mr_base = addr;
 		sc->mr_desc[d].mr_len = ffs(mask) << 17;
@@ -117,7 +117,7 @@ k6_mrinit(struct mem_range_softc *sc)
 		if (uc)
 			sc->mr_desc[d].mr_flags |= MDF_UNCACHEABLE;
 	}
-	
+
 	printf("mtrr: K6-family MTRR support (%d registers)\n", sc->mr_ndesc);
 }
 
@@ -160,7 +160,7 @@ k6_mrset(struct mem_range_softc *sc, struct mem_range_desc *desc, int *arg)
 	}
 
 out:
-	
+
 	s = intr_disable();
 	wbinvd();
 	reg = rdmsr(UWCCR);

sys/arch/i386/i386/lapic.c

@@ -151,7 +151,7 @@ lapic_set_lvt(void)
 		 * the local APIC timer dead, so we disable it by reading
 		 * the Interrupt Pending Message register and clearing both
 		 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
-		 * 
+		 *
 		 * Reference:
 		 *   "BIOS and Kernel Developer's Guide for AMD NPT
 		 *    Family 0Fh Processors"

sys/arch/i386/i386/machdep.c

@@ -1121,7 +1121,7 @@ cyrix3_cpu_setup(struct cpu_info *ci)
 		/*
 		 * C3 Nehemiah & later: fall through.
 		 */
-	
+
 	case 10: /* C7-M Type A */
 	case 13: /* C7-M Type D */
 	case 15: /* Nano */
@@ -1770,7 +1770,7 @@ identifycpu(struct cpu_info *ci)
 		 * with eax 0x01
 		 */
 
-		cpuid(0x01, regs); 
+		cpuid(0x01, regs);
 		ci->ci_cflushsz = ((regs[1] >> 8) & 0xff) * 8;
 	}
 
@@ -2263,7 +2263,7 @@ p3_get_bus_clock(struct cpu_info *ci)
 			goto print_msr;
 		}
 		break;
-	default: 
+	default:
 		/* no FSB on modern Intel processors */
 		break;
 	}
@@ -3170,7 +3170,7 @@ init386(paddr_t first_avail)
 	if (bios_memmap == NULL)
 		panic("no BIOS memory map supplied");
 #endif
- 
+
 	/*
 	 * account all the memory passed in the map from /boot
 	 * calculate avail_end and count the physmem.

sys/arch/i386/i386/mainbus.c

@@ -231,7 +231,7 @@ mainbus_attach(struct device *parent, struct device *self, void *aux)
 #if NPCI > 0
 	if (pci_mode_detect() != 0) {
 		pci_init_extents();
-		
+
 		bzero(&mba.mba_pba, sizeof(mba.mba_pba));
 		mba.mba_pba.pba_busname = "pci";
 		mba.mba_pba.pba_iot = I386_BUS_SPACE_IO;

sys/arch/i386/i386/mem.c

@@ -236,7 +236,7 @@ mmmmap(dev_t dev, off_t off, int prot)
 		default:
 			return -1;
 		}
-			
+
 #endif
 	default:
 		return -1;
@@ -276,7 +276,7 @@ mem_ioctl(dev_t dev, u_long cmd, caddr_t data, int flags, struct proc *p)
 	int nd, error = 0;
 	struct mem_range_op *mo = (struct mem_range_op *)data;
 	struct mem_range_desc *md;
-	
+
 	/* is this for us? */
 	if ((cmd != MEMRANGE_GET) &&
 	    (cmd != MEMRANGE_SET))
@@ -306,7 +306,7 @@ mem_ioctl(dev_t dev, u_long cmd, caddr_t data, int flags, struct proc *p)
 		}
 		mo->mo_arg[0] = nd;
 		break;
-		
+
 	case MEMRANGE_SET:
 		md = malloc(sizeof(struct mem_range_desc), M_MEMDESC, M_WAITOK);
 		error = copyin(mo->mo_desc, md, sizeof(struct mem_range_desc));

sys/arch/i386/i386/mptramp.s

@@ -151,7 +151,7 @@ _TRMP_LABEL(.Lmp_startup)
 	movl	%cr4,%eax
 	orl	$CR4_PAE,%eax
 	movl	%eax, %cr4
-	
+
 	movl	$MSR_EFER,%ecx
 	rdmsr
 	orl	$EFER_NXE, %eax

sys/arch/i386/i386/mtrr.c

@@ -51,7 +51,7 @@ mem_range_attach(void)
 	     (model == 0x8 &&
 	      step > 0x7))) {
 		mem_range_softc.mr_op = &k6_mrops;
-		
+
 		/* Try for i686 MTRRs */
 	} else if (((strcmp(cpu_vendor, "GenuineIntel") == 0) ||
 		    (strcmp(cpu_vendor, "CentaurHauls") == 0) ||

sys/arch/i386/i386/pctr.c

@@ -177,7 +177,7 @@ pctrioctl(dev_t dev, u_long cmd, caddr_t data, int fflag, struct proc *p)
 	case PCIOCRD:
 	{
 		struct pctrst *st = (struct pctrst *)data;
-		
+
 		if (usepctr)
 			pctrrd(st);
 		else if (usep5ctr)

sys/arch/i386/i386/pmap.c

@@ -577,7 +577,7 @@ pmap_exec_account(struct pmap *pm, vaddr_t va,
 
 	if ((opte ^ npte) & PG_X)
 		pmap_tlb_shootpage(pm, va);
-			
+
 	if (cpu_pae)
 		return;
 
@@ -1437,7 +1437,7 @@ pmap_destroy(struct pmap *pmap)
 		return;
 
 #ifdef MULTIPROCESSOR
-	pmap_tlb_droppmap(pmap);	
+	pmap_tlb_droppmap(pmap);
 #endif
 
 	mtx_enter(&pmaps_lock);
@@ -1639,7 +1639,7 @@ pmap_flush_cache(vaddr_t addr, vsize_t len)
 		wbinvd_on_all_cpus();
 		return;
 	}
-	
+
 	mfence();
 	for (i = addr; i < addr + len; i += curcpu()->ci_cflushsz)
 		clflush(i);
@@ -1660,7 +1660,7 @@ pmap_flush_page(paddr_t pa)
 	if (cpu_pae) {
 		pmap_flush_page_pae(pa);
 		return;
-	}	
+	}
 
 	pte = PTESLEW(flsh_pte, id);
 	va = VASLEW(pmap_flshp, id);
@@ -2864,7 +2864,7 @@ pmap_tlb_shootrange(struct pmap *pm, vaddr_t sva, vaddr_t eva)
 	vaddr_t va;
 
 	for (va = sva; va < eva; va += PAGE_SIZE)
-		pmap_update_pg(va);	
+		pmap_update_pg(va);
 }
 
 void

sys/arch/i386/i386/powernow-k7.c

@@ -359,9 +359,9 @@ k7pnow_acpi_init(struct k7pnow_cpu_state *cstate, uint64_t status)
 		return 0;
 
 	curs = k7pnow_acpi_states(cstate, pss, cstate->n_states, status);
-	/* 
+	/*
 	 * XXX: Some BIOS supplied _PSS implementations have the wrong
-	 * maximum frequency, if we encounter one of these punt and 
+	 * maximum frequency, if we encounter one of these punt and
 	 * hope the legacy tables have correct values.
 	 */
 	mfid = PN7_STA_MFID(status);

sys/arch/i386/i386/process_machdep.c

@@ -344,7 +344,7 @@ process_sstep(struct proc *p, int sstep)
 		tf->tf_eflags |= PSL_T;
 	else
 		tf->tf_eflags &= ~PSL_T;
-	
+
 	return (0);
 }
 

sys/arch/i386/i386/via.c

@@ -329,7 +329,7 @@ viac3_crypto_swauth(struct cryptop *crp, struct cryptodesc *crd,
 		type = CRYPTO_BUF_MBUF;
 	else
 		type= CRYPTO_BUF_IOV;
-		
+
 	return (swcr_authcompute(crp, crd, sw, buf, type));
 }
 

sys/arch/i386/include/cpu.h

@@ -84,8 +84,8 @@ struct cpu_info {
 	struct schedstate_percpu ci_schedstate; /* scheduler state */
 	struct cpu_info *ci_next;	/* next cpu */
 
-	/* 
-	 * Public members. 
+	/*
+	 * Public members.
 	 */
 	struct proc *ci_curproc; 	/* current owner of the processor */
 	cpuid_t ci_cpuid; 		/* our CPU ID */
@@ -178,7 +178,7 @@ struct cpu_info {
  * roles (mostly relating to hardclock handling); we distinguish
  * between the processor which booted us, and the processor currently
  * holding the "primary" role just to give us the flexibility later to
- * change primaries should we be sufficiently twisted.  
+ * change primaries should we be sufficiently twisted.
  */
 
 #define	CPUF_BSP	0x0001		/* CPU is the original BSP */
@@ -473,7 +473,7 @@ void	mp_setperf_init(void);
 int	cpu_paenable(void *);
 #endif /* _KERNEL */
 
-/* 
+/*
  * CTL_MACHDEP definitions.
  */
 #define	CPU_CONSDEV		1	/* dev_t: console terminal device */

sys/arch/i386/include/cpufunc.h

@@ -65,11 +65,11 @@ static __inline void wrmsr(u_int, u_int64_t);
 static __inline u_int64_t rdmsr(u_int);
 static __inline void breakpoint(void);
 
-static __inline void 
+static __inline void
 invlpg(u_int addr)
-{ 
+{
         __asm volatile("invlpg (%0)" : : "r" (addr) : "memory");
-}  
+}
 
 static __inline void
 lidt(void *p)
@@ -257,14 +257,14 @@ mwait(u_long extensions, u_int hints)
 	__asm volatile("mwait" : : "a" (hints), "c" (extensions));
 }
 
-/* 
+/*
  * Some of the undocumented AMD64 MSRs need a 'passcode' to access.
  *
  * See LinuxBIOSv2: src/cpu/amd/model_fxx/model_fxx_init.c
  */
 
 #define	OPTERON_MSR_PASSCODE	0x9c5a203a
- 
+
 static __inline u_int64_t
 rdmsr_locked(u_int msr, u_int code)
 {

sys/arch/i386/include/cpuvar.h

@@ -49,7 +49,7 @@
  *      Foundation, Inc. and its contributors.
  * 4. Neither the name of The NetBSD Foundation nor the names of its
  *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.  
+ *    from this software without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY
  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

sys/arch/i386/include/db_machdep.h

@@ -1,28 +1,28 @@
 /*	$OpenBSD: db_machdep.h,v 1.30 2021/08/30 08:11:12 jasper Exp $	*/
 /*	$NetBSD: db_machdep.h,v 1.9 1996/05/03 19:23:59 christos Exp $	*/
 
-/* 
+/*
  * Mach Operating System
  * Copyright (c) 1991,1990 Carnegie Mellon University
  * All Rights Reserved.
- * 
+ *
  * Permission to use, copy, modify and distribute this software and its
  * documentation is hereby granted, provided that both the copyright
  * notice and this permission notice appear in all copies of the
  * software, derivative works or modified versions, and any portions
  * thereof, and that both notices appear in supporting documentation.
- * 
+ *
  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
  * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
- * 
+ *
  * Carnegie Mellon requests users of this software to return to
- * 
+ *
  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
  *  School of Computer Science
  *  Carnegie Mellon University
  *  Pittsburgh PA 15213-3890
- * 
+ *
  * any improvements or extensions that they make and grant Carnegie Mellon
  * the rights to redistribute these changes.
  */

sys/arch/i386/include/i82093reg.h

@@ -59,7 +59,7 @@
 #define		IOAPIC_ID_MASK		0x0f000000
 
 /* Version, and maximum interrupt pin number. */
-  
+
 #define IOAPIC_VER		0x01
 
 #define		IOAPIC_VER_SHIFT		0

sys/arch/i386/include/i82093var.h

@@ -37,9 +37,9 @@
 
 #include <machine/apicvar.h>
 
-struct ioapic_pin 
+struct ioapic_pin
 {
-	struct intrhand		*ip_handler; 
+	struct intrhand		*ip_handler;
 	struct ioapic_pin	*ip_next; /* next pin on this vector */
 	struct mp_intr_map 	*ip_map;
 	int			ip_vector; /* IDT vector */
@@ -60,7 +60,7 @@ struct ioapic_softc {
 	volatile u_int32_t	*sc_reg;	/* KVA of ioapic addr */
 	volatile u_int32_t	*sc_data;	/* KVA of ioapic data */
 	struct ioapic_pin	*sc_pins;	/* sc_apic_sz entries */
-};      
+};
 
 /*
  * MP: intr_handle_t is bitfielded.
@@ -82,7 +82,7 @@ struct ioapic_softc {
 #define APIC_IRQ_PIN(x) ((x & APIC_INT_PIN_MASK) >> APIC_INT_PIN_SHIFT)
 
 void   *apic_intr_establish(int, int, int, int (*)(void *), void *,
-    const char *); 
+    const char *);
 void	apic_intr_disestablish(void *);
 
 void	ioapic_print_redir(struct ioapic_softc *, char *, int);

sys/arch/i386/include/ieeefp.h

@@ -1,6 +1,6 @@
 /*	$OpenBSD: ieeefp.h,v 1.3 2011/03/23 16:54:35 pirofti Exp $	*/
 
-/* 
+/*
  * Written by J.T. Conklin, Apr 6, 1995
  * Public domain.
  */

sys/arch/i386/include/intrdefs.h

@@ -41,7 +41,7 @@
  * XXX in various arrays of our implementation.  We are hoping that
  * XXX the context will provide enough information to not make this
  * XXX sloppy naming a real problem.
- * 
+ *
  * There are tty, network and disk drivers that use free() at interrupt
  * time, so imp > (tty | net | bio).
  *

sys/arch/i386/include/mpbiosreg.h

@@ -81,7 +81,7 @@ struct mpbios_fps {
 	u_int32_t	signature;
 /* string defined by the Intel MP Spec as identifying the MP table */
 #define MP_FP_SIG		0x5f504d5f	/* _MP_ */
-	
+
 	u_int32_t 	pap;
 	u_int8_t  	length;
 	u_int8_t  	spec_rev;
@@ -98,7 +98,7 @@ struct mpbios_fps {
 struct mpbios_cth {
 	u_int32_t	signature;
 #define MP_CT_SIG		0x504d4350 	/* PCMP */
-	
+
 	u_int16_t 	base_len;
 	u_int8_t  	spec_rev;
 	u_int8_t  	checksum;

sys/arch/i386/include/mpbiosvar.h

@@ -43,7 +43,7 @@
 
 #include <machine/mpbiosreg.h>
 
-struct mp_bus 
+struct mp_bus
 {
 	char *mb_name;		/* XXX bus name */
 	int mb_idx;		/* XXX bus index */

sys/arch/i386/include/pic.h

@@ -9,7 +9,7 @@
 
 struct cpu_info;
 
-/* 
+/*
  * Structure common to all PIC softcs
  */
 struct pic {

sys/arch/i386/include/pmap.h

@@ -349,7 +349,7 @@ vaddr_t pmap_tmpmap_pa_pae(paddr_t);
 void pmap_tmpunmap_pa_pae(void);
 
 
-/* 
+/*
  * functions for flushing the cache for vaddrs and pages.
  * these functions are not part of the MI pmap interface and thus
  * should not be used as such.

sys/arch/i386/include/profile.h

@@ -68,7 +68,7 @@ mcount(void)								\
 #ifdef _KERNEL
 /*
  * We inline the code that splhigh and splx would do here as otherwise we would
- * call recursively into mcount() as machdep.c is compiled with -pg on a 
+ * call recursively into mcount() as machdep.c is compiled with -pg on a
  * profiling build.
  */
 #define	MCOUNT_ENTER	_SPLRAISE(s, IPL_HIGH); __splbarrier()

sys/arch/i386/include/psl.h

@@ -94,5 +94,5 @@ extern int intr_shared_edge;	/* This system has shared edge interrupts */
 
 #endif /* _LOCORE */
 #endif /* _KERNEL */
- 
+
 #endif /* !_MACHINE_PSL_H_ */

sys/arch/i386/include/reloc.h

@@ -41,10 +41,10 @@
 #define RELOC_GOTOFF    	9   /* 32 bit offset to GOT */
 #define RELOC_GOTPC     	10  /* 32 bit PC relative offset to GOT */
 #define RELOC_TLS_TPOFF		14  /* negative offset in static TLS block */
-#define RELOC_16        	20 
-#define RELOC_PC16      	21 
-#define RELOC_8         	22 
-#define RELOC_PC8       	23 
+#define RELOC_16        	20
+#define RELOC_PC16      	21
+#define RELOC_8         	22
+#define RELOC_PC8       	23
 #define RELOC_TLS_DTPMOD32	35 /* ID of module containing symbol */
 #define RELOC_TLS_DTPOFF32	36 /* Offset in TLS block */
 #define RELOC_TLS_TPOFF32	37 /* Offset in static TLS block */

sys/arch/i386/include/segments.h

@@ -50,11 +50,11 @@
  */
 
 #define	ISPL(s)		((s) & SEL_RPL)	/* what is the priority level of a selector */
-#define	SEL_KPL		0		/* kernel privilege level */	
-#define	SEL_UPL		3		/* user privilege level */	
+#define	SEL_KPL		0		/* kernel privilege level */
+#define	SEL_UPL		3		/* user privilege level */
 #define	SEL_RPL		3		/* requester's privilege level mask */
 #define	ISLDT(s)	((s) & SEL_LDT)	/* is it local or global */
-#define	SEL_LDT		4		/* local descriptor table */	
+#define	SEL_LDT		4		/* local descriptor table */
 #define	IDXSEL(s)	(((s) >> 3) & 0x1fff)		/* index of selector */
 #define	GSEL(s,r)	(((s) << 3) | r)		/* a global selector */
 #define	LSEL(s,r)	(((s) << 3) | r | SEL_LDT)	/* a local selector */

sys/arch/i386/include/specialreg.h

@@ -558,7 +558,7 @@
  * NCRx+0: A31-A24 of starting address
  * NCRx+1: A23-A16 of starting address
  * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
- * 
+ *
  * The non-cacheable region's starting address must be aligned to the
  * size indicated by the NCR_SIZE_xx field.
  */

sys/arch/i386/isa/ahc_isa.c

@@ -150,7 +150,7 @@ ahc_isa_irq(bus_space_tag_t iot, bus_space_handle_t ioh)
 	int irq;
 	u_char intdef;
 	u_char hcntrl;
-	
+
 	/* Pause the card preserving the IRQ type */
 	hcntrl = bus_space_read_1(iot, ioh, HCNTRL) & IRQMS;
 	bus_space_write_1(iot, ioh, HCNTRL, hcntrl | PAUSE);
@@ -284,7 +284,7 @@ ahc_isa_match(struct isa_attach_args *ia, bus_addr_t iobase)
  */
 int
 ahc_isa_probe(struct device *parent, void *match, void *aux)
-{       
+{
 	struct isa_attach_args *ia = aux;
 	struct ahc_isa_slot *as;
 
@@ -341,15 +341,15 @@ ahc_isa_attach(struct device *parent, struct device *self, void *aux)
 	char idstring[EISA_IDSTRINGLEN];
 	const char *model;
 	u_int intdef;
-	
+
 	ahc_set_name(ahc, ahc->sc_dev.dv_xname);
 	ahc_set_unit(ahc, ahc->sc_dev.dv_unit);
-	
+
 	/* set dma tags */
 	ahc->parent_dmat = ia->ia_dmat;
-	
-	ahc->chip = AHC_VL; /* We are a VL Bus Controller */  
-	
+
+	ahc->chip = AHC_VL; /* We are a VL Bus Controller */
+
 	if (bus_space_map(iot, ia->ia_iobase, ia->ia_iosize, 0, &ioh))
 		panic("ahc_isa_attach: can't map slot i/o addresses");
 	if (!ahc_isa_idstring(iot, ioh, idstring))
@@ -365,13 +365,13 @@ ahc_isa_attach(struct device *parent, struct device *self, void *aux)
 		panic("ahc_isa_attach: Unknown device type %s", idstring);
 	}
 	printf(": %s\n", model);
-	
+
 	ahc->channel = 'A';
 	ahc->chip = AHC_AIC7770;
 	ahc->features = AHC_AIC7770_FE;
 	ahc->bugs |= AHC_TMODE_WIDEODD_BUG;
 	ahc->flags |= AHC_PAGESCBS;
-	
+
 	/* set tag and handle */
 	ahc->tag = iot;
 	ahc->bsh = ioh;
@@ -387,26 +387,26 @@ ahc_isa_attach(struct device *parent, struct device *self, void *aux)
 
 	if (ahc_reset(ahc, /*reinit*/FALSE) != 0)
 		return;
-	
+
 	/* See if we are edge triggered */
 	intdef = ahc_inb(ahc, INTDEF);
 	if ((intdef & EDGE_TRIG) != 0)
 		ahc->flags |= AHC_EDGE_INTERRUPT;
 
 	/*
-	 * Now that we know we own the resources we need, do the 
+	 * Now that we know we own the resources we need, do the
 	 * card initialization.
 	 */
 	aha2840_load_seeprom(ahc);
 
-	/*      
+	/*
 	 * See if we have a Rev E or higher aic7770. Anything below a
 	 * Rev E will have a R/O autoflush disable configuration bit.
 	 * It's still not clear exactly what is different about the Rev E.
 	 * We think it allows 8 bit entries in the QOUTFIFO to support
 	 * "paging" SCBs so you can have more than 4 commands active at
 	 * once.
-	 */     
+	 */
 	{
 		char *id_string;
 		u_char sblkctl;
@@ -448,7 +448,7 @@ ahc_isa_attach(struct device *parent, struct device *self, void *aux)
 		ahc_free(ahc);
 		return;
 	}
-	
+
 	/*
 	 * Link this softc in with all other ahc instances.
 	 */
@@ -474,7 +474,7 @@ ahc_isa_attach(struct device *parent, struct device *self, void *aux)
 	}
 
 	ahc_intr_enable(ahc, TRUE);
-	
+
 	/* Attach sub-devices - always succeeds */
 	ahc_attach(ahc);
 }
@@ -496,7 +496,7 @@ aha2840_load_seeprom(struct ahc_softc *ahc)
 	sd.sd_regsize = 1;
 	sd.sd_control_offset = SEECTL_2840;
 	sd.sd_status_offset = STATUS_2840;
-	sd.sd_dataout_offset = STATUS_2840;		
+	sd.sd_dataout_offset = STATUS_2840;
 	sd.sd_chip = C46;
 	sd.sd_MS = 0;
 	sd.sd_RDY = EEPROM_TF;
@@ -508,7 +508,7 @@ aha2840_load_seeprom(struct ahc_softc *ahc)
 	if (bootverbose)
 		printf("%s: Reading SEEPROM...", ahc_name(ahc));
 	have_seeprom = read_seeprom(&sd, 
-				    (u_int16_t *)&sc, 
+				    (u_int16_t *)&sc,
 				    /*start_addr*/0,
 				    sizeof(sc)/2);
 
@@ -565,7 +565,7 @@ aha2840_load_seeprom(struct ahc_softc *ahc)
 		if (sc.adapter_control & CFRESETB)
 			scsi_conf |= RESET_SCSI;
 
-		if (sc.bios_control & CF284XEXTEND)		
+		if (sc.bios_control & CF284XEXTEND)
 			ahc->flags |= AHC_EXTENDED_TRANS_A;
 		/* Set SCSICONF info */
 		ahc_outb(ahc, SCSICONF, scsi_conf);

sys/arch/i386/isa/clock.c

@@ -182,7 +182,7 @@ startclocks(void)
 
 	/* Check diagnostic status */
 	if ((s = mc146818_read(NULL, NVRAM_DIAG)) != 0)	/* XXX softc */
-		printf("RTC BIOS diagnostic error %b\n", (unsigned int) s, 
+		printf("RTC BIOS diagnostic error %b\n", (unsigned int) s,
 		    NVRAM_DIAG_BITS);
 }
 
@@ -578,7 +578,7 @@ rtcgettime(struct todr_chip_handle *handle, struct timeval *tv)
 	mc_todregs rtclk;
 	struct clock_ymdhms dt;
 	int s;
-	
+
 	s = splclock();
 	if (rtcget(&rtclk)) {
 		splx(s);

sys/arch/i386/isa/isa_machdep.c

@@ -169,7 +169,7 @@ isa_defaultirq(void)
 	for (i = 0; i < ICU_LEN; i++)
 		setgate(&idt[ICU_OFFSET + i], IDTVEC(intr)[i], 0,
 		    SDT_SYS386IGT, SEL_KPL, GICODE_SEL);
-  
+
 	/* initialize 8259's */
 	outb(IO_ICU1, 0x11);		/* reset; program device, four bytes */
 	outb(IO_ICU1+1, ICU_OFFSET);	/* starting at this vector index */
@@ -783,7 +783,7 @@ _isa_bus_dmamap_load(bus_dma_tag_t t, bus_dmamap_t map, void *buf,
 		cookie->id_origbuflen = buflen;
 		error = _bus_dmamap_load(t, map, cookie->id_bouncebuf,
 		    buflen, p, flags);
-		
+
 		if (error) {
 			/*
 			 * Free the bounce pages, unless our resources
@@ -799,7 +799,7 @@ _isa_bus_dmamap_load(bus_dma_tag_t t, bus_dmamap_t map, void *buf,
 		/*
 		 * Just use the generic load function.
 		 */
-		error = _bus_dmamap_load(t, map, buf, buflen, p, flags); 
+		error = _bus_dmamap_load(t, map, buf, buflen, p, flags);
 	}
 
 	return (error);

sys/arch/i386/isa/lms.c

@@ -82,7 +82,7 @@ lmsprobe(struct device *parent, void *match, void *aux)
 	bus_space_tag_t iot = ia->ia_iot;
 	bus_space_handle_t ioh;
 	int rv;
-	
+
 	/* Disallow wildcarded i/o base. */
 	if (ia->ia_iobase == IOBASEUNK)
 		return 0;

sys/arch/i386/isa/npx.c

@@ -217,7 +217,7 @@ npxprobe1(struct isa_attach_args *ia)
 		/*
 		 * Good, now check for a proper control word.
 		 */
-		control = 0x5a5a;	
+		control = 0x5a5a;
 		fnstcw(&control);
 		if ((control & 0x1f3f) == 0x033f) {
 			/*

sys/arch/i386/pci/ali1543.c

@@ -71,18 +71,18 @@
  *    notice, this list of conditions and the following disclaimer.
  * 2. The name of the developer may NOT be used to endorse or promote products
  *    derived from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
- * SUCH DAMAGE. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
  */
 
 /* HAYAKAWA Koichi wrote ALi 1543 PCI ICU code basing on VIA82C586 driver */

sys/arch/i386/pci/glxsb.c

@@ -167,7 +167,7 @@ struct glxsb_softc {
 	struct glxsb_session	*sc_sessions;
 #endif /* CRYPTO */
 
-	uint64_t		save_gld_msr;	
+	uint64_t		save_gld_msr;
 };
 
 int	glxsb_match(struct device *, void *, void *);
@@ -624,7 +624,7 @@ glxsb_crypto_swauth(struct cryptop *crp, struct cryptodesc *crd,
 		type = CRYPTO_BUF_MBUF;
 	else
 		type = CRYPTO_BUF_IOV;
-		
+
 	return (swcr_authcompute(crp, crd, sw, buf, type));
 }
 
@@ -638,7 +638,7 @@ glxsb_crypto_swenc(struct cryptop *crp, struct cryptodesc *crd,
 		type = CRYPTO_BUF_MBUF;
 	else
 		type = CRYPTO_BUF_IOV;
-		
+
 	return (swcr_encdec(crd, sw, buf, type));
 }
 

sys/arch/i386/pci/ichpcib.c

@@ -187,7 +187,7 @@ ichss_present(struct pci_attach_args *pa)
 	/*
 	 * This form of SpeedStep works only with certain Intel processors.
 	 * However, other processors can be coupled with these ICH southbridges
-	 * causing false positives. This heuristic comes partly from the 
+	 * causing false positives. This heuristic comes partly from the
 	 * Linux speedstep-ich driver.
 	 */
 	if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801DBM_LPC ||

sys/arch/i386/pci/opti82c558.c

@@ -42,18 +42,18 @@
  *    notice, this list of conditions and the following disclaimer.
  * 2. The name of the developer may NOT be used to endorse or promote products
  *    derived from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
- * SUCH DAMAGE. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
  */
 
 /*

sys/arch/i386/pci/opti82c558reg.h

@@ -12,18 +12,18 @@
  *    notice, this list of conditions and the following disclaimer.
  * 2. The name of the developer may NOT be used to endorse or promote products
  *    derived from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
- * SUCH DAMAGE. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
  */
 
 /*

sys/arch/i386/pci/opti82c700.c

@@ -42,18 +42,18 @@
  *    notice, this list of conditions and the following disclaimer.
  * 2. The name of the developer may NOT be used to endorse or promote products
  *    derived from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
- * SUCH DAMAGE. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
  */
 
 /*

sys/arch/i386/pci/opti82c700reg.h

@@ -12,18 +12,18 @@
  *    notice, this list of conditions and the following disclaimer.
  * 2. The name of the developer may NOT be used to endorse or promote products
  *    derived from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
- * SUCH DAMAGE. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
  */
 
 /*

sys/arch/i386/pci/pci_addr_fixup.c

@@ -78,12 +78,12 @@ void
 pci_addr_fixup(struct pcibios_softc *sc, pci_chipset_tag_t pc, int maxbus)
 {
 	extern paddr_t avail_end;
-	const char *verbose_header = 
+	const char *verbose_header =
 		"[%s]-----------------------\n"
 		"  device vendor product\n"
 		"  register space address    size\n"
 		"--------------------------------------------\n";
-	const char *verbose_footer = 
+	const char *verbose_footer =
 		"--------------------------[%3d devices bogus]\n";
 
 	const struct {
@@ -106,7 +106,7 @@ pci_addr_fixup(struct pcibios_softc *sc, pci_chipset_tag_t pc, int maxbus)
 	    PCIADDR_PORT_START, PCIADDR_PORT_END, M_DEVBUF, 0, 0, EX_NOWAIT);
 	KASSERT(sc->extent_port);
 
-	/* 
+	/*
 	 * 1. check & reserve system BIOS setting.
 	 */
 	PCIBIOS_PRINTV((verbose_header, "System BIOS Setting"));
@@ -114,19 +114,19 @@ pci_addr_fixup(struct pcibios_softc *sc, pci_chipset_tag_t pc, int maxbus)
 	pci_device_foreach(sc, pc, maxbus, pciaddr_resource_reserve_disabled);
 	PCIBIOS_PRINTV((verbose_footer, sc->nbogus));
 
-	/* 
+	/*
 	 * 2. reserve non-PCI area.
 	 */
 	for (srp = system_reserve; srp->size; srp++) {
 		error = extent_alloc_region(sc->extent_mem, srp->start,
-		    srp->size, EX_NOWAIT| EX_MALLOCOK);	
+		    srp->size, EX_NOWAIT| EX_MALLOCOK);
 		if (error != 0)
 			printf("WARNING: can't reserve area for %s.\n",
 			       srp->name);
 	}
 
-	/* 
-	 * 3. determine allocation space 
+	/*
+	 * 3. determine allocation space
 	 */
 	start = round_page(avail_end + 1);
 	if (start < PCIADDR_ISAMEM_RESERVE)
@@ -136,8 +136,8 @@ pci_addr_fixup(struct pcibios_softc *sc, pci_chipset_tag_t pc, int maxbus)
 	PCIBIOS_PRINTV((" Physical memory end: 0x%08lx\n PCI memory mapped I/O "
 	    "space start: 0x%08lx\n", avail_end, sc->mem_alloc_start));
 
-	/* 
-	 * 4. do fixup 
+	/*
+	 * 4. do fixup
 	 */
 	PCIBIOS_PRINTV((verbose_header, "PCIBIOS fixup stage"));
 	sc->nbogus = 0;
@@ -191,7 +191,7 @@ pciaddr_resource_manage(struct pcibios_softc *sc, pci_chipset_tag_t pc,
 		    PCI_HDRTYPE_TYPE(val));
 		sc->nbogus++;
 		return;
-	case 0: 
+	case 0:
 		reg_start = PCI_MAPREG_START;
 		reg_end   = PCI_MAPREG_END;
 		break;
@@ -205,7 +205,7 @@ pciaddr_resource_manage(struct pcibios_softc *sc, pci_chipset_tag_t pc,
 		break;
 	}
 	error = 0;
-    
+
 	for (mapreg = reg_start; mapreg < reg_end; mapreg += width) {
 		/* inquire PCI device bus space requirement */
 		val = pci_conf_read(pc, tag, mapreg);
@@ -213,20 +213,20 @@ pciaddr_resource_manage(struct pcibios_softc *sc, pci_chipset_tag_t pc,
 
 		mask = pci_conf_read(pc, tag, mapreg);
 		pci_conf_write(pc, tag, mapreg, val);
-	
+
 		type = PCI_MAPREG_TYPE(val);
 		width = 4;
 		if (type == PCI_MAPREG_TYPE_MEM) {
-			if (PCI_MAPREG_MEM_TYPE(val) == 
+			if (PCI_MAPREG_MEM_TYPE(val) ==
 			    PCI_MAPREG_MEM_TYPE_64BIT) {
 				/* XXX We could examine the upper 32 bits
-				 * XXX of the BAR here, but we are totally 
-				 * XXX unprepared to handle a non-zero value, 
-				 * XXX either here or anywhere else in 
-				 * XXX i386-land. 
+				 * XXX of the BAR here, but we are totally
+				 * XXX unprepared to handle a non-zero value,
+				 * XXX either here or anywhere else in
+				 * XXX i386-land.
 				 * XXX So just arrange to not look at the
 				 * XXX upper 32 bits, lest we misinterpret
-				 * XXX it as a 32-bit BAR set to zero. 
+				 * XXX it as a 32-bit BAR set to zero.
 				 */
 			    width = 8;
 			}
@@ -239,15 +239,15 @@ pciaddr_resource_manage(struct pcibios_softc *sc, pci_chipset_tag_t pc,
 			size = PCI_MAPREG_IO_SIZE(mask);
 			ex = sc->extent_port;
 		}
-	
+
 		if (!size) /* unused register */
 			continue;
 
 		/* reservation/allocation phase */
 		error += (*func) (sc, pc, tag, mapreg, ex, type, &addr, size);
 
-		PCIBIOS_PRINTV(("\t%02xh %s 0x%08x 0x%08x\n", 
-				mapreg, type ? "port" : "mem ", 
+		PCIBIOS_PRINTV(("\t%02xh %s 0x%08x 0x%08x\n",
+				mapreg, type ? "port" : "mem ",
 				(unsigned int)addr, (unsigned int)size));
 	}
 
@@ -264,14 +264,14 @@ pciaddr_do_resource_allocate(struct pcibios_softc *sc, pci_chipset_tag_t pc,
 {
 	bus_addr_t start;
 	int error;
-	
+
 	if (*addr) /* no need to allocate */
 		return (0);
 
 	/* XXX Don't allocate if device is AGP device to avoid conflict. */
-	if (pciaddr_device_is_agp(pc, tag)) 
+	if (pciaddr_device_is_agp(pc, tag))
 		return (0);
-	
+
 	start = (type == PCI_MAPREG_TYPE_MEM ? sc->mem_alloc_start
 		: sc->port_alloc_start);
 	if (start < ex->ex_start || start + size - 1 >= ex->ex_end) {
@@ -375,12 +375,12 @@ pciaddr_ioaddr(u_int32_t val)
 void
 pciaddr_print_devid(pci_chipset_tag_t pc, pcitag_t tag)
 {
-	int bus, device, function;	
+	int bus, device, function;
 	pcireg_t id;
-	
+
 	id = pci_conf_read(pc, tag, PCI_ID_REG);
 	pci_decompose_tag(pc, tag, &bus, &device, &function);
-	printf("%03d:%02d:%d %04x:%04x\n", bus, device, function, 
+	printf("%03d:%02d:%d %04x:%04x\n", bus, device, function,
 	       PCI_VENDOR(id), PCI_PRODUCT(id));
 }
 
@@ -400,7 +400,7 @@ pciaddr_device_is_agp(pci_chipset_tag_t pc, pcitag_t tag)
 			    off != 0;
 			    off = PCI_CAPLIST_NEXT(rval) ) {
 				rval = pci_conf_read(pc, tag, off);
-				if (PCI_CAPLIST_CAP(rval) == PCI_CAP_AGP) 
+				if (PCI_CAPLIST_CAP(rval) == PCI_CAP_AGP)
 					return (1);
 			}
 		}

sys/arch/i386/pci/pci_bus_fixup.c

@@ -12,18 +12,18 @@
  *    notice, this list of conditions and the following disclaimer.
  * 2. The name of the developer may NOT be used to endorse or promote products
  *    derived from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
- * SUCH DAMAGE. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
  */
 
 /*
@@ -256,11 +256,11 @@ pci_bus_fixup(pci_chipset_tag_t pc, int bus)
 void
 pcibus_print_devid(pci_chipset_tag_t pc, pcitag_t tag)
 {
-	int bus, device, function;	
+	int bus, device, function;
 	pcireg_t id;
 
 	id = pci_conf_read(pc, tag, PCI_ID_REG);
 	pci_decompose_tag(pc, tag, &bus, &device, &function);
-	printf("%03d:%02d:%d %04x:%04x\n", bus, device, function, 
+	printf("%03d:%02d:%d %04x:%04x\n", bus, device, function,
 	       PCI_VENDOR(id), PCI_PRODUCT(id));
 }

sys/arch/i386/pci/pci_machdep.c

@@ -175,7 +175,7 @@ struct {
  */
 struct bus_dma_tag pci_bus_dma_tag = {
 	NULL,			/* _cookie */
-	_bus_dmamap_create, 
+	_bus_dmamap_create,
 	_bus_dmamap_destroy,
 	_bus_dmamap_load,
 	_bus_dmamap_load_mbuf,
@@ -595,7 +595,7 @@ pci_mode_detect(void)
 	return (pci_mode);
 not1:
 	outl(PCI_MODE1_ADDRESS_REG, sav);
- 
+
 	/*
 	 * This mode 2 check is quite weak (and known to give false
 	 * positives on some Compaq machines).
@@ -865,7 +865,7 @@ pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level,
 
 #if NIOAPIC > 0
 	if (l != -1 && ih.line & APIC_INT_VIA_APIC)
-		return (apic_intr_establish(ih.line, IST_LEVEL, level, func, 
+		return (apic_intr_establish(ih.line, IST_LEVEL, level, func,
 		    arg, what));
 #endif
 	if (l == 0 || l >= ICU_LEN || l == 2)
@@ -888,7 +888,7 @@ pci_intr_disestablish(pci_chipset_tag_t pc, void *cookie)
 		pcitag_t tag = { .mode1 = ih->ih_pin };
 		pcireg_t reg;
 		int off;
-		
+
 		if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, &reg))
 			pci_conf_write(pc, tag, off, reg &= ~PCI_MSI_MC_MSIE);
 

sys/arch/i386/pci/pcibios.c

@@ -66,18 +66,18 @@
  *    notice, this list of conditions and the following disclaimer.
  * 2. The name of the developer may NOT be used to endorse or promote products
  *    derived from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
- * SUCH DAMAGE. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
  */
 
 /*
@@ -253,7 +253,7 @@ pcibios_pir_init(struct pcibios_softc *sc)
 		if (pirh->signature != BIOS32_MAKESIG('$', 'P', 'I', 'R') &&
 		    pirh->signature != BIOS32_MAKESIG('_', 'P', 'I', 'R'))
 			continue;
-		
+
 		if (pirh->tablesize < sizeof(*pirh))
 			continue;
 

sys/arch/i386/pci/pciide_gcsc_reg.h

@@ -27,7 +27,7 @@
  */
 
 
-/* 
+/*
  * 6.4 - ATA-5 Controller Register Definitions.
  */
 #define GCSC_MSR_ATAC_BASE 		0x51300000

sys/arch/i386/pci/pciide_machdep.c

@@ -146,7 +146,7 @@ gcsc_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
 		pciide_unmap_compat_intr(pa, cp, 0, interface);
 		return;
 	}
-	
+
 	gcsc_setup_channel(&cp->wdc_channel);
 }
 

sys/arch/i386/pci/piix.c

@@ -42,18 +42,18 @@
  *    notice, this list of conditions and the following disclaimer.
  * 2. The name of the developer may NOT be used to endorse or promote products
  *    derived from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
- * SUCH DAMAGE. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
  */
 
 /*

sys/arch/i386/pci/piixreg.h

@@ -12,18 +12,18 @@
  *    notice, this list of conditions and the following disclaimer.
  * 2. The name of the developer may NOT be used to endorse or promote products
  *    derived from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
- * SUCH DAMAGE. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
  */
 
 /*

sys/arch/i386/pci/piixvar.h

@@ -42,18 +42,18 @@
  *    notice, this list of conditions and the following disclaimer.
  * 2. The name of the developer may NOT be used to endorse or promote products
  *    derived from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
- * SUCH DAMAGE. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
  */
 
 /*

sys/arch/i386/pci/rccosb4reg.h

@@ -12,18 +12,18 @@
  *    notice, this list of conditions and the following disclaimer.
  * 2. The name of the developer may NOT be used to endorse or promote products
  *    derived from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
- * SUCH DAMAGE. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
  */
 
 /*

sys/arch/i386/pci/sis85c503.c

@@ -42,18 +42,18 @@
  *    notice, this list of conditions and the following disclaimer.
  * 2. The name of the developer may NOT be used to endorse or promote products
  *    derived from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
- * SUCH DAMAGE. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
  */
 
 /*

sys/arch/i386/pci/sis85c503reg.h

@@ -12,18 +12,18 @@
  *    notice, this list of conditions and the following disclaimer.
  * 2. The name of the developer may NOT be used to endorse or promote products
  *    derived from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
- * SUCH DAMAGE. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
  */
 
 /*

sys/arch/i386/pci/via82c586.c

@@ -42,18 +42,18 @@
  *    notice, this list of conditions and the following disclaimer.
  * 2. The name of the developer may NOT be used to endorse or promote products
  *    derived from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
- * SUCH DAMAGE. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
  */
 
 /*
@@ -117,7 +117,7 @@ via82c586_init(pci_chipset_tag_t pc, bus_space_tag_t iot, pcitag_t tag,
 
 	if (piix_init(pc, iot, tag, ptagp, phandp) == 0) {
 		*ptagp = &via82c586_pci_icu;
-		
+
 		/*
 		 * Enable EISA ELCR.
 		 */

sys/arch/i386/pci/via82c586reg.h

@@ -12,18 +12,18 @@
  *    notice, this list of conditions and the following disclaimer.
  * 2. The name of the developer may NOT be used to endorse or promote products
  *    derived from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
- * SUCH DAMAGE. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
  */
 
 /*

sys/arch/i386/stand/biosboot/biosboot.S

@@ -15,8 +15,8 @@
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
@@ -164,7 +164,7 @@ _start:
 
 	. = _start + 3
 
-	.asciz	"OpenBSD"
+	.asciz	"SecBSD"
 
 	/* BPB */
 	. = _start + 0x0b

sys/arch/i386/stand/boot/Makefile

@@ -54,7 +54,7 @@ SRCS+=	aes_xts.c bcrypt_pbkdf.c blowfish.c explicit_bzero.c hmac_sha1.c \
 .endif
 
 .PATH:	${S}/lib/libkern
-SRCS+=	ashldi3.c ashrdi3.c divdi3.c lshrdi3.c moddi3.c qdivrem.c 
+SRCS+=	ashldi3.c ashrdi3.c divdi3.c lshrdi3.c moddi3.c qdivrem.c
 SRCS+=	strlcpy.c
 
 .PATH:	${S}/lib/libz

sys/arch/i386/stand/boot/conf.c

@@ -13,8 +13,8 @@
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

sys/arch/i386/stand/boot/srt0.S

@@ -13,8 +13,8 @@
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

sys/arch/i386/stand/cdboot/conf.c

@@ -14,8 +14,8 @@
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

sys/arch/i386/stand/cdboot/srt0.S

@@ -13,8 +13,8 @@
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
@@ -199,7 +199,7 @@ ENTRY(debugchar)
 
 	xorl	%eax, %eax
 	movb	12(%esp), %al
-	
+
 	andl	$0xfffffffe, %ebx
 	movb	%al, (%ebx)
 	popl	%ebx

sys/arch/i386/stand/libsa/biosdev.c

@@ -578,7 +578,7 @@ biosopen(struct open_file *f, ...)
 		return 0;
 	}
 #endif
- 
+
 	for (maj = 0; maj < nbdevs &&
 	    strncmp(dev, bdevs[maj], devlen); maj++);
 	if (maj >= nbdevs) {

sys/arch/i386/stand/libsa/biosdev.h

@@ -13,8 +13,8 @@
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

sys/arch/i386/stand/libsa/debug.h

@@ -13,8 +13,8 @@
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

sys/arch/i386/stand/libsa/debug_i386.S

@@ -13,8 +13,8 @@
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

sys/arch/i386/stand/libsa/debug_md.h

@@ -13,8 +13,8 @@
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

sys/arch/i386/stand/libsa/disk.h

@@ -13,8 +13,8 @@
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

sys/arch/i386/stand/libsa/gidt.S

@@ -13,8 +13,8 @@
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
@@ -195,7 +195,7 @@ pmm_init:
 	idte(mc)
 	idte(xx); idte(xx); idte(xx);  idte(xx); idte(xx); idte(xx)
 	idte(xx); idte(xx); idte(xx);  idte(xx); idte(xx); idte(xx)
-	idte(xx) 
+	idte(xx)
 	/* BIOS entry points (32-63) */
 	idtb(0);  idtb(1);  idtb(2);  idtb(3);  idtb(4);  idtb(5)
 	idtb(6);  idtb(7);  idtb(8);  idtb(9);  idtb(10); idtb(11)

sys/arch/i386/stand/libsa/gidt.h

@@ -14,8 +14,8 @@
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

sys/arch/i386/stand/libsa/mdrandom.c

@@ -1,7 +1,7 @@
 /*	$OpenBSD: mdrandom.c,v 1.3 2020/06/19 15:00:45 naddy Exp $	*/
 
 /*
- * Copyright (c) 2020 Theo de Raadt 
+ * Copyright (c) 2020 Theo de Raadt
  *
  * Permission to use, copy, modify, and distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above

sys/arch/i386/stand/libsa/pciprobe.c

@@ -13,8 +13,8 @@
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL