sync with OpenBSD -current
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0f27a61c5c
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F42C07F07E2E35B7
46 changed files with 425 additions and 338 deletions
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@ -53,7 +53,6 @@ static bool is_fru_eeprom_supported(struct amdgpu_device *adev)
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*/
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switch (adev->asic_type) {
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case CHIP_VEGA20:
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#ifdef notyet
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/* D161 and D163 are the VG20 server SKUs */
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if (strnstr(atom_ctx->vbios_version, "D161",
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sizeof(atom_ctx->vbios_version)) ||
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@ -61,13 +60,11 @@ static bool is_fru_eeprom_supported(struct amdgpu_device *adev)
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sizeof(atom_ctx->vbios_version)))
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return true;
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else
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#endif
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return false;
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case CHIP_ALDEBARAN:
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/* All Aldebaran SKUs have the FRU */
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return true;
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case CHIP_SIENNA_CICHLID:
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#ifdef notyet
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if (strnstr(atom_ctx->vbios_version, "D603",
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sizeof(atom_ctx->vbios_version))) {
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if (strnstr(atom_ctx->vbios_version, "D603GLXE",
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@ -78,9 +75,6 @@ static bool is_fru_eeprom_supported(struct amdgpu_device *adev)
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} else {
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return false;
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}
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#else
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return false;
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#endif
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default:
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return false;
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}
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@ -2327,13 +2327,11 @@ static void amdgpu_ras_get_quirks(struct amdgpu_device *adev)
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if (!ctx)
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return;
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#ifdef notyet
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if (strnstr(ctx->vbios_version, "D16406",
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sizeof(ctx->vbios_version)) ||
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strnstr(ctx->vbios_version, "D36002",
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sizeof(ctx->vbios_version)))
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adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX);
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#endif
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}
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/*
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@ -149,44 +149,29 @@ static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev,
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/* VEGA20 and ARCTURUS */
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if (adev->asic_type == CHIP_VEGA20)
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control->i2c_address = EEPROM_I2C_MADDR_0;
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#ifdef notyet
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else if (strnstr(atom_ctx->vbios_version,
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"D342",
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sizeof(atom_ctx->vbios_version)))
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control->i2c_address = EEPROM_I2C_MADDR_0;
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else
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control->i2c_address = EEPROM_I2C_MADDR_4;
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#else
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STUB();
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control->i2c_address = EEPROM_I2C_MADDR_4;
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#endif
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return true;
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case IP_VERSION(11, 0, 7):
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control->i2c_address = EEPROM_I2C_MADDR_0;
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return true;
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case IP_VERSION(13, 0, 2):
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#ifdef notyet
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if (strnstr(atom_ctx->vbios_version, "D673",
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sizeof(atom_ctx->vbios_version)))
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control->i2c_address = EEPROM_I2C_MADDR_4;
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else
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control->i2c_address = EEPROM_I2C_MADDR_0;
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#else
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STUB();
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control->i2c_address = EEPROM_I2C_MADDR_0;
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#endif
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return true;
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case IP_VERSION(13, 0, 0):
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#ifdef notyet
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if (strnstr(atom_ctx->vbios_pn, "D707",
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sizeof(atom_ctx->vbios_pn)))
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control->i2c_address = EEPROM_I2C_MADDR_0;
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else
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control->i2c_address = EEPROM_I2C_MADDR_4;
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#else
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STUB();
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control->i2c_address = EEPROM_I2C_MADDR_4;
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#endif
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return true;
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case IP_VERSION(13, 0, 6):
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case IP_VERSION(13, 0, 10):
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@ -631,13 +631,14 @@ static void amdgpu_vm_pt_free(struct amdgpu_vm_bo_base *entry)
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if (!entry->bo)
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return;
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entry->bo->vm_bo = NULL;
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shadow = amdgpu_bo_shadowed(entry->bo);
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if (shadow) {
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ttm_bo_set_bulk_move(&shadow->tbo, NULL);
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amdgpu_bo_unref(&shadow);
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}
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ttm_bo_set_bulk_move(&entry->bo->tbo, NULL);
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entry->bo->vm_bo = NULL;
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spin_lock(&entry->vm->status_lock);
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list_del(&entry->vm_status);
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@ -1690,6 +1690,32 @@ static void sdma_v5_2_get_clockgating_state(void *handle, u64 *flags)
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*flags |= AMD_CG_SUPPORT_SDMA_LS;
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}
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static void sdma_v5_2_ring_begin_use(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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/* SDMA 5.2.3 (RMB) FW doesn't seem to properly
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* disallow GFXOFF in some cases leading to
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* hangs in SDMA. Disallow GFXOFF while SDMA is active.
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* We can probably just limit this to 5.2.3,
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* but it shouldn't hurt for other parts since
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* this GFXOFF will be disallowed anyway when SDMA is
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* active, this just makes it explicit.
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*/
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amdgpu_gfx_off_ctrl(adev, false);
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}
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static void sdma_v5_2_ring_end_use(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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/* SDMA 5.2.3 (RMB) FW doesn't seem to properly
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* disallow GFXOFF in some cases leading to
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* hangs in SDMA. Allow GFXOFF when SDMA is complete.
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*/
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amdgpu_gfx_off_ctrl(adev, true);
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}
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const struct amd_ip_funcs sdma_v5_2_ip_funcs = {
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.name = "sdma_v5_2",
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.early_init = sdma_v5_2_early_init,
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@ -1738,6 +1764,8 @@ static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = {
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.test_ib = sdma_v5_2_ring_test_ib,
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.insert_nop = sdma_v5_2_ring_insert_nop,
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.pad_ib = sdma_v5_2_ring_pad_ib,
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.begin_use = sdma_v5_2_ring_begin_use,
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.end_use = sdma_v5_2_ring_end_use,
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.emit_wreg = sdma_v5_2_ring_emit_wreg,
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.emit_reg_wait = sdma_v5_2_ring_emit_reg_wait,
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.emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait,
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