sync code with last improvements from OpenBSD
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F42C07F07E2E35B7
8 changed files with 257 additions and 85 deletions
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@ -1,4 +1,4 @@
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/* $OpenBSD: ytphy.c,v 1.3 2023/07/08 08:18:30 kettenis Exp $ */
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/* $OpenBSD: ytphy.c,v 1.4 2023/09/01 20:35:31 kettenis Exp $ */
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/*
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* Copyright (c) 2001 Theo de Raadt
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* Copyright (c) 2023 Mark Kettenis <kettenis@openbsd.org>
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@ -57,12 +57,22 @@
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#define YT8521_EXT_CHIP_CONFIG 0xa001
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#define YT8521_RXC_DLY_EN (1 << 8)
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#define YT8521_CFG_LDO_MASK (0x3 << 4)
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#define YT8521_CFG_LDO_3V3 0x0
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#define YT8521_CFG_LDO_2V5 0x1
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#define YT8521_CFG_LDO_1V8 0x2 /* or 0x3 */
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#define YT8521_EXT_RGMII_CONFIG1 0xa003
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#define YT8521_TX_CLK_SEL (1 << 14)
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#define YT8521_RX_DELAY_SEL_MASK (0xf << 10)
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#define YT8521_RX_DELAY_SEL_SHIFT 10
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#define YT8521_TX_DELAY_SEL_MASK (0xf << 0)
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#define YT8521_TX_DELAY_SEL_SHIFT 0
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#define YT8521_EXT_PAD_DRIVE_STRENGTH 0xa010
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#define YT8531_RGMII_RXC_DS_MASK (0x7 << 13)
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#define YT8531_RGMII_RXC_DS_SHIFT 13
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#define YT8531_RGMII_RXD_DS_MASK ((0x1 << 12) | (0x3 << 4))
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#define YT8531_RGMII_RXD_DS_LOW(x) (((x) & 0x3) << 4)
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#define YT8531_RGMII_RXD_DS_HIGH(x) (((x) >> 2) << 12)
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int ytphy_match(struct device *, void *, void *);
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void ytphy_attach(struct device *, struct device *, void *);
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@ -79,6 +89,7 @@ int ytphy_service(struct mii_softc *, struct mii_data *, int);
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void ytphy_yt8511_init(struct mii_softc *);
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void ytphy_yt8521_init(struct mii_softc *);
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void ytphy_yt8521_update(struct mii_softc *);
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void ytphy_yt8531_init(struct mii_softc *);
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const struct mii_phy_funcs ytphy_funcs = {
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ytphy_service, ukphy_status, mii_phy_reset,
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@ -138,8 +149,10 @@ ytphy_attach(struct device *parent, struct device *self, void *aux)
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if (ma->mii_id1 == 0x0000 && ma->mii_id2 == 0x010a)
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ytphy_yt8511_init(sc);
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else
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else if (ma->mii_id1 == 0x0000 && ma->mii_id2 == 0x011a)
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ytphy_yt8521_init(sc);
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else
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ytphy_yt8531_init(sc);
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sc->mii_capabilities =
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PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
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@ -362,3 +375,97 @@ ytphy_yt8521_update(struct mii_softc *sc)
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PHY_WRITE(sc, YT8511_REG_ADDR, addr);
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#endif
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}
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/* The RGMII drive strength depends on the voltage level. */
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struct ytphy_ds_map {
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uint32_t volt; /* mV */
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uint16_t amp; /* uA */
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uint16_t ds;
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};
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struct ytphy_ds_map ytphy_yt8531_ds_map[] = {
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{ 1800, 1200, 0 },
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{ 1800, 2100, 1 },
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{ 1800, 2700, 2 },
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{ 1800, 2910, 3 },
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{ 1800, 3110, 4 },
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{ 1800, 3600, 5 },
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{ 1800, 3970, 6 },
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{ 1800, 4350, 7 },
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{ 3300, 3070, 0 },
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{ 3300, 4080, 1 },
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{ 3300, 4370, 2 },
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{ 3300, 4680, 3 },
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{ 3300, 5020, 4 },
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{ 3300, 5450, 5 },
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{ 3300, 5740, 6 },
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{ 3300, 6140, 7 },
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};
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uint32_t
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ytphy_yt8531_ds(struct mii_softc *sc, uint32_t volt, uint32_t amp)
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{
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int i;
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for (i = 0; i < nitems(ytphy_yt8531_ds_map); i++) {
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if (ytphy_yt8531_ds_map[i].volt == volt &&
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ytphy_yt8531_ds_map[i].amp == amp)
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return ytphy_yt8531_ds_map[i].ds;
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}
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if (amp) {
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printf("%s: unknown drive strength (%d uA at %d mV)\n",
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sc->mii_dev.dv_xname, amp, volt);
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}
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/* Default drive strength. */
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return 3;
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}
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void
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ytphy_yt8531_init(struct mii_softc *sc)
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{
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uint32_t rx_clk_drv = 0;
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uint32_t rx_data_drv = 0;
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uint16_t addr, data;
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uint16_t volt;
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ytphy_yt8521_init(sc);
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#ifdef __HAVE_FDT
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if (sc->mii_pdata->mii_node) {
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rx_clk_drv = OF_getpropint(sc->mii_pdata->mii_node,
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"motorcomm,rx-clk-drv-microamp", 0);
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rx_data_drv = OF_getpropint(sc->mii_pdata->mii_node,
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"motorcomm,rx-data-drv-microamp", 0);
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}
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#endif
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/* Save address register. */
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addr = PHY_READ(sc, YT8511_REG_ADDR);
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PHY_WRITE(sc, YT8511_REG_ADDR, YT8521_EXT_CHIP_CONFIG);
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data = PHY_READ(sc, YT8511_REG_DATA);
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if ((data & YT8521_CFG_LDO_MASK) == YT8521_CFG_LDO_3V3)
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volt = 3300;
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else if ((data & YT8521_CFG_LDO_MASK) == YT8521_CFG_LDO_2V5)
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volt = 2500;
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else
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volt = 1800;
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rx_clk_drv = ytphy_yt8531_ds(sc, volt, rx_clk_drv);
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rx_data_drv = ytphy_yt8531_ds(sc, volt, rx_data_drv);
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PHY_WRITE(sc, YT8511_REG_ADDR, YT8521_EXT_PAD_DRIVE_STRENGTH);
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data = PHY_READ(sc, YT8511_REG_DATA);
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data &= ~YT8531_RGMII_RXC_DS_MASK;
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data |= rx_clk_drv << YT8531_RGMII_RXC_DS_SHIFT;
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data &= ~YT8531_RGMII_RXD_DS_MASK;
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data |= YT8531_RGMII_RXD_DS_LOW(rx_data_drv);
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data |= YT8531_RGMII_RXD_DS_HIGH(rx_data_drv);
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PHY_WRITE(sc, YT8511_REG_DATA, data);
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/* Restore address register. */
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PHY_WRITE(sc, YT8511_REG_ADDR, addr);
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}
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@ -1,4 +1,4 @@
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/* $OpenBSD: if_umb.c,v 1.54 2023/08/29 23:28:38 dlg Exp $ */
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/* $OpenBSD: if_umb.c,v 1.55 2023/09/01 20:24:29 mvs Exp $ */
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/*
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* Copyright (c) 2016 genua mbH
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@ -1851,7 +1851,6 @@ umb_add_inet_config(struct umb_softc *sc, struct in_addr ip, u_int prefixlen,
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info.rti_info[RTAX_GATEWAY] = sintosa(&ifra.ifra_dstaddr);
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rv = rtrequest(RTM_ADD, &info, 0, &rt, ifp->if_rdomain);
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NET_UNLOCK();
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if (rv) {
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printf("%s: unable to set IPv4 default route, "
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"error %d\n", DEVNAM(ifp->if_softc), rv);
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@ -1862,6 +1861,7 @@ umb_add_inet_config(struct umb_softc *sc, struct in_addr ip, u_int prefixlen,
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rtm_send(rt, RTM_ADD, rv, ifp->if_rdomain);
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rtfree(rt);
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}
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NET_UNLOCK();
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if (ifp->if_flags & IFF_DEBUG) {
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char str[3][INET_ADDRSTRLEN];
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@ -1932,7 +1932,6 @@ umb_add_inet6_config(struct umb_softc *sc, struct in6_addr *ip, u_int prefixlen,
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info.rti_info[RTAX_GATEWAY] = sin6tosa(&ifra.ifra_dstaddr);
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rv = rtrequest(RTM_ADD, &info, 0, &rt, ifp->if_rdomain);
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NET_UNLOCK();
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if (rv) {
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printf("%s: unable to set IPv6 default route, "
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"error %d\n", DEVNAM(ifp->if_softc), rv);
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@ -1943,6 +1942,7 @@ umb_add_inet6_config(struct umb_softc *sc, struct in6_addr *ip, u_int prefixlen,
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rtm_send(rt, RTM_ADD, rv, ifp->if_rdomain);
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rtfree(rt);
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}
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NET_UNLOCK();
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if (ifp->if_flags & IFF_DEBUG) {
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char str[3][INET6_ADDRSTRLEN];
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