sync with OpenBSD -current
This commit is contained in:
parent
8801582927
commit
30cf31d90d
GPG key ID:
F42C07F07E2E35B7
55 changed files with 633 additions and 516 deletions
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@ -1,4 +1,4 @@
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/* $OpenBSD: param.h,v 1.28 2019/12/23 21:42:01 bluhm Exp $ */
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/* $OpenBSD: param.h,v 1.29 2023/12/14 13:26:49 claudio Exp $ */
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/*-
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* Copyright (c) 1990 The Regents of the University of California.
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@ -73,12 +73,6 @@
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#define MSGBUFSIZE (32 * PAGE_SIZE) /* default message buffer size */
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#endif
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/*
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* Maximum size of the kernel malloc arena in PAGE_SIZE-sized
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* logical pages.
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*/
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#define NKMEMPAGES_MAX_DEFAULT ((128 * 1024 * 1024) >> PAGE_SHIFT)
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#define __HAVE_ACPI
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#endif /* _KERNEL */
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@ -1,4 +1,4 @@
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/* $OpenBSD: param.h,v 1.24 2018/09/14 13:58:20 claudio Exp $ */
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/* $OpenBSD: param.h,v 1.25 2023/12/14 13:26:49 claudio Exp $ */
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/*
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* Copyright (c) 1994,1995 Mark Brinicombe.
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@ -57,12 +57,6 @@
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#define NMBCLUSTERS (32 * 1024) /* max cluster allocation */
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/*
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* Maximum size of the kernel malloc arena in PAGE_SIZE-sized
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* logical pages.
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*/
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#define NKMEMPAGES_MAX_DEFAULT ((64 * 1024 * 1024) >> PAGE_SHIFT)
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/* Constants used to divide the USPACE area */
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/*
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* The USPACE area contains :
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@ -1,4 +1,4 @@
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/* $OpenBSD: param.h,v 1.6 2018/09/14 13:58:20 claudio Exp $ */
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/* $OpenBSD: param.h,v 1.7 2023/12/14 13:26:49 claudio Exp $ */
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/*-
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* Copyright (c) 1990 The Regents of the University of California.
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@ -69,12 +69,6 @@
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#define MSGBUFSIZE (16 * PAGE_SIZE) /* default message buffer size */
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#endif
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/*
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* Maximum size of the kernel malloc arena in PAGE_SIZE-sized
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* logical pages.
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*/
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#define NKMEMPAGES_MAX_DEFAULT ((128 * 1024 * 1024) >> PAGE_SHIFT)
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#define STACKALIGNBYTES (16 - 1)
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#define STACKALIGN(p) ((u_long)(p) &~ STACKALIGNBYTES)
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@ -1,4 +1,4 @@
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/* $OpenBSD: param.h,v 1.52 2023/11/08 18:59:01 mglocker Exp $ */
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/* $OpenBSD: param.h,v 1.53 2023/12/14 13:26:49 claudio Exp $ */
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/*-
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* Copyright (c) 1990 The Regents of the University of California.
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@ -73,12 +73,6 @@
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#define MSGBUFSIZE (8 * PAGE_SIZE) /* default message buffer size */
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#endif
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/*
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* Maximum size of the kernel malloc arena in PAGE_SIZE-sized
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* logical pages.
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*/
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#define NKMEMPAGES_MAX_DEFAULT ((128 * 1024 * 1024) >> PAGE_SHIFT)
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#define __HAVE_ACPI
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#endif /* _KERNEL */
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@ -201,7 +201,7 @@ static int amdgpu_cs_pass1(struct amdgpu_cs_parser *p,
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}
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for (i = 0; i < p->nchunks; i++) {
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struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
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struct drm_amdgpu_cs_chunk __user *chunk_ptr = NULL;
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struct drm_amdgpu_cs_chunk user_chunk;
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uint32_t __user *cdata;
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@ -90,7 +90,7 @@ static void amdgpu_display_flip_work_func(struct work_struct *__work)
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struct drm_crtc *crtc = &amdgpu_crtc->base;
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unsigned long flags;
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unsigned i;
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unsigned int i;
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int vpos, hpos;
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for (i = 0; i < work->shared_count; ++i)
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@ -167,7 +167,7 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
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u64 tiling_flags;
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int i, r;
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work = kzalloc(sizeof *work, GFP_KERNEL);
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work = kzalloc(sizeof(*work), GFP_KERNEL);
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if (work == NULL)
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return -ENOMEM;
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@ -298,18 +298,17 @@ int amdgpu_display_crtc_set_config(struct drm_mode_set *set,
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adev = drm_to_adev(dev);
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/* if we have active crtcs and we don't have a power ref,
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take the current one */
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* take the current one
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*/
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if (active && !adev->have_disp_power_ref) {
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adev->have_disp_power_ref = true;
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return ret;
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}
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/* if we have no active crtcs, then drop the power ref
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we got before */
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if (!active && adev->have_disp_power_ref) {
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pm_runtime_put_autosuspend(dev->dev);
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/* if we have no active crtcs, then go to
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* drop the power ref we got before
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*/
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if (!active && adev->have_disp_power_ref)
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adev->have_disp_power_ref = false;
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}
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out:
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/* drop the power reference we got coming in here */
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pm_runtime_put_autosuspend(dev->dev);
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@ -473,11 +472,10 @@ bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector,
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if (amdgpu_connector->router.ddc_valid)
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amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
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if (use_aux) {
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if (use_aux)
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ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2);
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} else {
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else
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ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2);
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}
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if (ret != 2)
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/* Couldn't find an accessible DDC on this connector */
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@ -486,10 +484,12 @@ bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector,
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* EDID header starts with:
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* 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
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* Only the first 6 bytes must be valid as
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* drm_edid_block_valid() can fix the last 2 bytes */
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* drm_edid_block_valid() can fix the last 2 bytes
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*/
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if (drm_edid_header_is_valid(buf) < 6) {
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/* Couldn't find an accessible EDID on this
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* connector */
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* connector
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*/
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return false;
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}
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return true;
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@ -1204,8 +1204,10 @@ amdgpu_display_user_framebuffer_create(struct drm_device *dev,
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obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
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if (obj == NULL) {
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drm_dbg_kms(dev, "No GEM object associated to handle 0x%08X, "
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"can't create framebuffer\n", mode_cmd->handles[0]);
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drm_dbg_kms(dev,
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"No GEM object associated to handle 0x%08X, can't create framebuffer\n",
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mode_cmd->handles[0]);
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return ERR_PTR(-ENOENT);
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}
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@ -1398,6 +1400,7 @@ bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
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}
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if (amdgpu_crtc->rmx_type != RMX_OFF) {
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fixed20_12 a, b;
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a.full = dfixed_const(src_v);
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b.full = dfixed_const(dst_v);
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amdgpu_crtc->vsc.full = dfixed_div(a, b);
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@ -1417,7 +1420,7 @@ bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
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*
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* \param dev Device to query.
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* \param pipe Crtc to query.
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* \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
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* \param flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
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* For driver internal use only also supports these flags:
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*
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* USE_REAL_VBLANKSTART to use the real start of vblank instead
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@ -1493,8 +1496,8 @@ int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev,
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/* Called from driver internal vblank counter query code? */
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if (flags & GET_DISTANCE_TO_VBLANKSTART) {
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/* Caller wants distance from real vbl_start in *hpos */
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*hpos = *vpos - vbl_start;
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/* Caller wants distance from real vbl_start in *hpos */
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*hpos = *vpos - vbl_start;
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}
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/* Fudge vblank to start a few scanlines earlier to handle the
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@ -1516,7 +1519,7 @@ int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev,
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/* In vblank? */
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if (in_vbl)
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ret |= DRM_SCANOUTPOS_IN_VBLANK;
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ret |= DRM_SCANOUTPOS_IN_VBLANK;
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/* Called from driver internal vblank counter query code? */
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if (flags & GET_DISTANCE_TO_VBLANKSTART) {
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@ -1622,6 +1625,7 @@ int amdgpu_display_suspend_helper(struct amdgpu_device *adev)
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if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
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struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
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r = amdgpu_bo_reserve(aobj, true);
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if (r == 0) {
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amdgpu_bo_unpin(aobj);
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@ -1629,9 +1633,9 @@ int amdgpu_display_suspend_helper(struct amdgpu_device *adev)
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}
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}
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if (fb == NULL || fb->obj[0] == NULL) {
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if (!fb || !fb->obj[0])
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continue;
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}
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robj = gem_to_amdgpu_bo(fb->obj[0]);
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if (!amdgpu_display_robj_is_fb(adev, robj)) {
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r = amdgpu_bo_reserve(robj, true);
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@ -1658,6 +1662,7 @@ int amdgpu_display_resume_helper(struct amdgpu_device *adev)
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if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
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struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
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r = amdgpu_bo_reserve(aobj, true);
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if (r == 0) {
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r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
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@ -79,6 +79,8 @@
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* That is, for an I2C EEPROM driver everything is controlled by
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* the "eeprom_addr".
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*
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* See also top of amdgpu_ras_eeprom.c.
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*
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* P.S. If you need to write, lock and read the Identification Page,
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* (M24M02-DR device only, which we do not use), change the "7" to
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* "0xF" in the macro below, and let the client set bit 20 to 1 in
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@ -33,12 +33,29 @@
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#include "amdgpu_reset.h"
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#define EEPROM_I2C_MADDR_VEGA20 0x0
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#define EEPROM_I2C_MADDR_ARCTURUS 0x40000
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#define EEPROM_I2C_MADDR_ARCTURUS_D342 0x0
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#define EEPROM_I2C_MADDR_SIENNA_CICHLID 0x0
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#define EEPROM_I2C_MADDR_ALDEBARAN 0x0
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#define EEPROM_I2C_MADDR_SMU_13_0_0 (0x54UL << 16)
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/* These are memory addresses as would be seen by one or more EEPROM
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* chips strung on the I2C bus, usually by manipulating pins 1-3 of a
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* set of EEPROM devices. They form a continuous memory space.
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*
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* The I2C device address includes the device type identifier, 1010b,
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* which is a reserved value and indicates that this is an I2C EEPROM
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* device. It also includes the top 3 bits of the 19 bit EEPROM memory
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* address, namely bits 18, 17, and 16. This makes up the 7 bit
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* address sent on the I2C bus with bit 0 being the direction bit,
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* which is not represented here, and sent by the hardware directly.
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*
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* For instance,
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* 50h = 1010000b => device type identifier 1010b, bits 18:16 = 000b, address 0.
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* 54h = 1010100b => --"--, bits 18:16 = 100b, address 40000h.
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* 56h = 1010110b => --"--, bits 18:16 = 110b, address 60000h.
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* Depending on the size of the I2C EEPROM device(s), bits 18:16 may
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* address memory in a device or a device on the I2C bus, depending on
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* the status of pins 1-3. See top of amdgpu_eeprom.c.
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*
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* The RAS table lives either at address 0 or address 40000h of EEPROM.
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*/
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#define EEPROM_I2C_MADDR_0 0x0
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#define EEPROM_I2C_MADDR_4 0x40000
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/*
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* The 2 macros bellow represent the actual size in bytes that
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@ -90,37 +107,23 @@
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static bool __is_ras_eeprom_supported(struct amdgpu_device *adev)
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{
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return adev->asic_type == CHIP_VEGA20 ||
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adev->asic_type == CHIP_ARCTURUS ||
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adev->asic_type == CHIP_SIENNA_CICHLID ||
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adev->asic_type == CHIP_ALDEBARAN;
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}
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static bool __get_eeprom_i2c_addr_arct(struct amdgpu_device *adev,
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struct amdgpu_ras_eeprom_control *control)
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{
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STUB();
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return false;
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#ifdef notyet
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struct atom_context *atom_ctx = adev->mode_info.atom_context;
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if (!control || !atom_ctx)
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switch (adev->ip_versions[MP1_HWIP][0]) {
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case IP_VERSION(11, 0, 2): /* VEGA20 and ARCTURUS */
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case IP_VERSION(11, 0, 7): /* Sienna cichlid */
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case IP_VERSION(13, 0, 0):
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case IP_VERSION(13, 0, 2): /* Aldebaran */
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case IP_VERSION(13, 0, 6):
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case IP_VERSION(13, 0, 10):
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return true;
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default:
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return false;
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if (strnstr(atom_ctx->vbios_version,
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"D342",
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sizeof(atom_ctx->vbios_version)))
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control->i2c_address = EEPROM_I2C_MADDR_ARCTURUS_D342;
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else
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control->i2c_address = EEPROM_I2C_MADDR_ARCTURUS;
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return true;
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#endif
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}
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}
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static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev,
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struct amdgpu_ras_eeprom_control *control)
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{
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struct atom_context *atom_ctx = adev->mode_info.atom_context;
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u8 i2c_addr;
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if (!control)
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@ -141,36 +144,57 @@ static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev,
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return true;
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}
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switch (adev->asic_type) {
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case CHIP_VEGA20:
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control->i2c_address = EEPROM_I2C_MADDR_VEGA20;
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break;
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case CHIP_ARCTURUS:
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return __get_eeprom_i2c_addr_arct(adev, control);
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case CHIP_SIENNA_CICHLID:
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control->i2c_address = EEPROM_I2C_MADDR_SIENNA_CICHLID;
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break;
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case CHIP_ALDEBARAN:
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control->i2c_address = EEPROM_I2C_MADDR_ALDEBARAN;
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break;
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||||
switch (adev->ip_versions[MP1_HWIP][0]) {
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case IP_VERSION(11, 0, 2):
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/* VEGA20 and ARCTURUS */
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if (adev->asic_type == CHIP_VEGA20)
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control->i2c_address = EEPROM_I2C_MADDR_0;
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#ifdef notyet
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else if (strnstr(atom_ctx->vbios_version,
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"D342",
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||||
sizeof(atom_ctx->vbios_version)))
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control->i2c_address = EEPROM_I2C_MADDR_0;
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else
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control->i2c_address = EEPROM_I2C_MADDR_4;
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#else
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STUB();
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control->i2c_address = EEPROM_I2C_MADDR_4;
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#endif
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return true;
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case IP_VERSION(11, 0, 7):
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control->i2c_address = EEPROM_I2C_MADDR_0;
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return true;
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case IP_VERSION(13, 0, 2):
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#ifdef notyet
|
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if (strnstr(atom_ctx->vbios_version, "D673",
|
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sizeof(atom_ctx->vbios_version)))
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control->i2c_address = EEPROM_I2C_MADDR_4;
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else
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control->i2c_address = EEPROM_I2C_MADDR_0;
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||||
#else
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STUB();
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control->i2c_address = EEPROM_I2C_MADDR_0;
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||||
#endif
|
||||
return true;
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||||
case IP_VERSION(13, 0, 0):
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||||
#ifdef notyet
|
||||
if (strnstr(atom_ctx->vbios_pn, "D707",
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||||
sizeof(atom_ctx->vbios_pn)))
|
||||
control->i2c_address = EEPROM_I2C_MADDR_0;
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||||
else
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||||
control->i2c_address = EEPROM_I2C_MADDR_4;
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#else
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STUB();
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control->i2c_address = EEPROM_I2C_MADDR_4;
|
||||
#endif
|
||||
return true;
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||||
case IP_VERSION(13, 0, 6):
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||||
case IP_VERSION(13, 0, 10):
|
||||
control->i2c_address = EEPROM_I2C_MADDR_4;
|
||||
return true;
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||||
default:
|
||||
return false;
|
||||
}
|
||||
|
||||
switch (adev->ip_versions[MP1_HWIP][0]) {
|
||||
case IP_VERSION(13, 0, 0):
|
||||
control->i2c_address = EEPROM_I2C_MADDR_SMU_13_0_0;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static void
|
||||
|
|
|
|||
|
|
@ -397,7 +397,7 @@ static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
|
|||
adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
|
||||
cpu_ptr = &adev->wb.wb[index];
|
||||
|
||||
r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib);
|
||||
r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);
|
||||
if (r) {
|
||||
DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
|
||||
goto err1;
|
||||
|
|
|
|||
|
|
@ -883,8 +883,8 @@ static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
|
|||
gpu_addr = adev->wb.gpu_addr + (index * 4);
|
||||
adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
|
||||
memset(&ib, 0, sizeof(ib));
|
||||
r = amdgpu_ib_get(adev, NULL, 16,
|
||||
AMDGPU_IB_POOL_DIRECT, &ib);
|
||||
|
||||
r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);
|
||||
if (r)
|
||||
goto err1;
|
||||
|
||||
|
|
|
|||
|
|
@ -1034,8 +1034,8 @@ static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
|
|||
gpu_addr = adev->wb.gpu_addr + (index * 4);
|
||||
adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
|
||||
memset(&ib, 0, sizeof(ib));
|
||||
r = amdgpu_ib_get(adev, NULL, 16,
|
||||
AMDGPU_IB_POOL_DIRECT, &ib);
|
||||
|
||||
r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);
|
||||
if (r)
|
||||
goto err1;
|
||||
|
||||
|
|
|
|||
|
|
@ -1500,6 +1500,13 @@ static void gen11_dsi_post_disable(struct intel_atomic_state *state,
|
|||
static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector,
|
||||
struct drm_display_mode *mode)
|
||||
{
|
||||
struct drm_i915_private *i915 = to_i915(connector->dev);
|
||||
enum drm_mode_status status;
|
||||
|
||||
status = intel_cpu_transcoder_mode_valid(i915, mode);
|
||||
if (status != MODE_OK)
|
||||
return status;
|
||||
|
||||
/* FIXME: DSC? */
|
||||
return intel_dsi_mode_valid(connector, mode);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -343,8 +343,13 @@ intel_crt_mode_valid(struct drm_connector *connector,
|
|||
struct drm_device *dev = connector->dev;
|
||||
struct drm_i915_private *dev_priv = to_i915(dev);
|
||||
int max_dotclk = dev_priv->max_dotclk_freq;
|
||||
enum drm_mode_status status;
|
||||
int max_clock;
|
||||
|
||||
status = intel_cpu_transcoder_mode_valid(dev_priv, mode);
|
||||
if (status != MODE_OK)
|
||||
return status;
|
||||
|
||||
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
|
||||
return MODE_NO_DBLESCAN;
|
||||
|
||||
|
|
|
|||
|
|
@ -8229,6 +8229,16 @@ intel_mode_valid(struct drm_device *dev,
|
|||
mode->vtotal > vtotal_max)
|
||||
return MODE_V_ILLEGAL;
|
||||
|
||||
return MODE_OK;
|
||||
}
|
||||
|
||||
enum drm_mode_status intel_cpu_transcoder_mode_valid(struct drm_i915_private *dev_priv,
|
||||
const struct drm_display_mode *mode)
|
||||
{
|
||||
/*
|
||||
* Additional transcoder timing limits,
|
||||
* excluding BXT/GLK DSI transcoders.
|
||||
*/
|
||||
if (DISPLAY_VER(dev_priv) >= 5) {
|
||||
if (mode->hdisplay < 64 ||
|
||||
mode->htotal - mode->hdisplay < 32)
|
||||
|
|
|
|||
|
|
@ -556,6 +556,9 @@ enum drm_mode_status
|
|||
intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
|
||||
const struct drm_display_mode *mode,
|
||||
bool bigjoiner);
|
||||
enum drm_mode_status
|
||||
intel_cpu_transcoder_mode_valid(struct drm_i915_private *i915,
|
||||
const struct drm_display_mode *mode);
|
||||
enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
|
||||
bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
|
||||
bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state);
|
||||
|
|
|
|||
|
|
@ -973,8 +973,9 @@ intel_dp_mode_valid(struct drm_connector *_connector,
|
|||
enum drm_mode_status status;
|
||||
bool dsc = false, bigjoiner = false;
|
||||
|
||||
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
|
||||
return MODE_NO_DBLESCAN;
|
||||
status = intel_cpu_transcoder_mode_valid(dev_priv, mode);
|
||||
if (status != MODE_OK)
|
||||
return status;
|
||||
|
||||
if (mode->flags & DRM_MODE_FLAG_DBLCLK)
|
||||
return MODE_H_ILLEGAL;
|
||||
|
|
|
|||
|
|
@ -703,6 +703,10 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
|
|||
return 0;
|
||||
}
|
||||
|
||||
*status = intel_cpu_transcoder_mode_valid(dev_priv, mode);
|
||||
if (*status != MODE_OK)
|
||||
return 0;
|
||||
|
||||
if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
|
||||
*status = MODE_NO_DBLESCAN;
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -225,10 +225,16 @@ intel_dvo_mode_valid(struct drm_connector *connector,
|
|||
{
|
||||
struct intel_connector *intel_connector = to_intel_connector(connector);
|
||||
struct intel_dvo *intel_dvo = intel_attached_dvo(intel_connector);
|
||||
struct drm_i915_private *i915 = to_i915(intel_connector->base.dev);
|
||||
const struct drm_display_mode *fixed_mode =
|
||||
intel_panel_fixed_mode(intel_connector, mode);
|
||||
int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
|
||||
int target_clock = mode->clock;
|
||||
enum drm_mode_status status;
|
||||
|
||||
status = intel_cpu_transcoder_mode_valid(i915, mode);
|
||||
if (status != MODE_OK)
|
||||
return status;
|
||||
|
||||
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
|
||||
return MODE_NO_DBLESCAN;
|
||||
|
|
|
|||
|
|
@ -1987,8 +1987,9 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
|
|||
bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state);
|
||||
bool ycbcr_420_only;
|
||||
|
||||
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
|
||||
return MODE_NO_DBLESCAN;
|
||||
status = intel_cpu_transcoder_mode_valid(dev_priv, mode);
|
||||
if (status != MODE_OK)
|
||||
return status;
|
||||
|
||||
if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
|
||||
clock *= 2;
|
||||
|
|
|
|||
|
|
@ -92,9 +92,9 @@ bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv,
|
|||
|
||||
/* asserts want to know the pipe even if the port is disabled */
|
||||
if (HAS_PCH_CPT(dev_priv))
|
||||
*pipe = (val & LVDS_PIPE_SEL_MASK_CPT) >> LVDS_PIPE_SEL_SHIFT_CPT;
|
||||
*pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK_CPT, val);
|
||||
else
|
||||
*pipe = (val & LVDS_PIPE_SEL_MASK) >> LVDS_PIPE_SEL_SHIFT;
|
||||
*pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK, val);
|
||||
|
||||
return val & LVDS_PORT_EN;
|
||||
}
|
||||
|
|
@ -389,11 +389,16 @@ intel_lvds_mode_valid(struct drm_connector *connector,
|
|||
struct drm_display_mode *mode)
|
||||
{
|
||||
struct intel_connector *intel_connector = to_intel_connector(connector);
|
||||
struct drm_i915_private *i915 = to_i915(intel_connector->base.dev);
|
||||
const struct drm_display_mode *fixed_mode =
|
||||
intel_panel_fixed_mode(intel_connector, mode);
|
||||
int max_pixclk = to_i915(connector->dev)->max_dotclk_freq;
|
||||
enum drm_mode_status status;
|
||||
|
||||
status = intel_cpu_transcoder_mode_valid(i915, mode);
|
||||
if (status != MODE_OK)
|
||||
return status;
|
||||
|
||||
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
|
||||
return MODE_NO_DBLESCAN;
|
||||
|
||||
|
|
|
|||
|
|
@ -115,7 +115,6 @@ struct intel_sdvo {
|
|||
|
||||
enum port port;
|
||||
|
||||
bool has_hdmi_monitor;
|
||||
bool has_hdmi_audio;
|
||||
|
||||
/* DDC bus used by this SDVO encoder */
|
||||
|
|
@ -1278,10 +1277,13 @@ static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config)
|
|||
pipe_config->clock_set = true;
|
||||
}
|
||||
|
||||
static bool intel_has_hdmi_sink(struct intel_sdvo *sdvo,
|
||||
static bool intel_has_hdmi_sink(struct intel_sdvo_connector *intel_sdvo_connector,
|
||||
const struct drm_connector_state *conn_state)
|
||||
{
|
||||
return sdvo->has_hdmi_monitor &&
|
||||
struct drm_connector *connector = conn_state->connector;
|
||||
|
||||
return intel_sdvo_connector->is_hdmi &&
|
||||
connector->display_info.is_hdmi &&
|
||||
READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI;
|
||||
}
|
||||
|
||||
|
|
@ -1360,7 +1362,7 @@ static int intel_sdvo_compute_config(struct intel_encoder *encoder,
|
|||
pipe_config->pixel_multiplier =
|
||||
intel_sdvo_get_pixel_multiplier(adjusted_mode);
|
||||
|
||||
pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo, conn_state);
|
||||
pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo_connector, conn_state);
|
||||
|
||||
if (pipe_config->has_hdmi_sink) {
|
||||
if (intel_sdvo_state->base.force_audio == HDMI_AUDIO_AUTO)
|
||||
|
|
@ -1871,13 +1873,19 @@ static enum drm_mode_status
|
|||
intel_sdvo_mode_valid(struct drm_connector *connector,
|
||||
struct drm_display_mode *mode)
|
||||
{
|
||||
struct drm_i915_private *i915 = to_i915(connector->dev);
|
||||
struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector));
|
||||
struct intel_sdvo_connector *intel_sdvo_connector =
|
||||
to_intel_sdvo_connector(connector);
|
||||
int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
|
||||
bool has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo, connector->state);
|
||||
bool has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo_connector, connector->state);
|
||||
int max_dotclk = i915->max_dotclk_freq;
|
||||
enum drm_mode_status status;
|
||||
int clock = mode->clock;
|
||||
|
||||
status = intel_cpu_transcoder_mode_valid(i915, mode);
|
||||
if (status != MODE_OK)
|
||||
return status;
|
||||
|
||||
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
|
||||
return MODE_NO_DBLESCAN;
|
||||
|
||||
|
|
@ -2064,7 +2072,6 @@ intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
|
|||
if (edid->input & DRM_EDID_INPUT_DIGITAL) {
|
||||
status = connector_status_connected;
|
||||
if (intel_sdvo_connector->is_hdmi) {
|
||||
intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
|
||||
intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
|
||||
}
|
||||
} else
|
||||
|
|
@ -2116,7 +2123,6 @@ intel_sdvo_detect(struct drm_connector *connector, bool force)
|
|||
|
||||
intel_sdvo->attached_output = response;
|
||||
|
||||
intel_sdvo->has_hdmi_monitor = false;
|
||||
intel_sdvo->has_hdmi_audio = false;
|
||||
|
||||
if ((intel_sdvo_connector->output_flag & response) == 0)
|
||||
|
|
|
|||
|
|
@ -956,8 +956,14 @@ static enum drm_mode_status
|
|||
intel_tv_mode_valid(struct drm_connector *connector,
|
||||
struct drm_display_mode *mode)
|
||||
{
|
||||
struct drm_i915_private *i915 = to_i915(connector->dev);
|
||||
const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state);
|
||||
int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
|
||||
int max_dotclk = i915->max_dotclk_freq;
|
||||
enum drm_mode_status status;
|
||||
|
||||
status = intel_cpu_transcoder_mode_valid(i915, mode);
|
||||
if (status != MODE_OK)
|
||||
return status;
|
||||
|
||||
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
|
||||
return MODE_NO_DBLESCAN;
|
||||
|
|
|
|||
|
|
@ -1627,9 +1627,25 @@ static const struct drm_encoder_funcs intel_dsi_funcs = {
|
|||
.destroy = intel_dsi_encoder_destroy,
|
||||
};
|
||||
|
||||
static enum drm_mode_status vlv_dsi_mode_valid(struct drm_connector *connector,
|
||||
struct drm_display_mode *mode)
|
||||
{
|
||||
struct drm_i915_private *i915 = to_i915(connector->dev);
|
||||
|
||||
if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
|
||||
enum drm_mode_status status;
|
||||
|
||||
status = intel_cpu_transcoder_mode_valid(i915, mode);
|
||||
if (status != MODE_OK)
|
||||
return status;
|
||||
}
|
||||
|
||||
return intel_dsi_mode_valid(connector, mode);
|
||||
}
|
||||
|
||||
static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
|
||||
.get_modes = intel_dsi_get_modes,
|
||||
.mode_valid = intel_dsi_mode_valid,
|
||||
.mode_valid = vlv_dsi_mode_valid,
|
||||
.atomic_check = intel_digital_connector_atomic_check,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -2681,52 +2681,50 @@
|
|||
* Enables the LVDS port. This bit must be set before DPLLs are enabled, as
|
||||
* the DPLL semantics change when the LVDS is assigned to that pipe.
|
||||
*/
|
||||
#define LVDS_PORT_EN (1 << 31)
|
||||
#define LVDS_PORT_EN REG_BIT(31)
|
||||
/* Selects pipe B for LVDS data. Must be set on pre-965. */
|
||||
#define LVDS_PIPE_SEL_SHIFT 30
|
||||
#define LVDS_PIPE_SEL_MASK (1 << 30)
|
||||
#define LVDS_PIPE_SEL(pipe) ((pipe) << 30)
|
||||
#define LVDS_PIPE_SEL_SHIFT_CPT 29
|
||||
#define LVDS_PIPE_SEL_MASK_CPT (3 << 29)
|
||||
#define LVDS_PIPE_SEL_CPT(pipe) ((pipe) << 29)
|
||||
#define LVDS_PIPE_SEL_MASK REG_BIT(30)
|
||||
#define LVDS_PIPE_SEL(pipe) REG_FIELD_PREP(LVDS_PIPE_SEL_MASK, (pipe))
|
||||
#define LVDS_PIPE_SEL_MASK_CPT REG_GENMASK(30, 29)
|
||||
#define LVDS_PIPE_SEL_CPT(pipe) REG_FIELD_PREP(LVDS_PIPE_SEL_MASK_CPT, (pipe))
|
||||
/* LVDS dithering flag on 965/g4x platform */
|
||||
#define LVDS_ENABLE_DITHER (1 << 25)
|
||||
#define LVDS_ENABLE_DITHER REG_BIT(25)
|
||||
/* LVDS sync polarity flags. Set to invert (i.e. negative) */
|
||||
#define LVDS_VSYNC_POLARITY (1 << 21)
|
||||
#define LVDS_HSYNC_POLARITY (1 << 20)
|
||||
#define LVDS_VSYNC_POLARITY REG_BIT(21)
|
||||
#define LVDS_HSYNC_POLARITY REG_BIT(20)
|
||||
|
||||
/* Enable border for unscaled (or aspect-scaled) display */
|
||||
#define LVDS_BORDER_ENABLE (1 << 15)
|
||||
#define LVDS_BORDER_ENABLE REG_BIT(15)
|
||||
/*
|
||||
* Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
|
||||
* pixel.
|
||||
*/
|
||||
#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
|
||||
#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
|
||||
#define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
|
||||
#define LVDS_A0A2_CLKA_POWER_MASK REG_GENMASK(9, 8)
|
||||
#define LVDS_A0A2_CLKA_POWER_DOWN REG_FIELD_PREP(LVDS_A0A2_CLKA_POWER_MASK, 0)
|
||||
#define LVDS_A0A2_CLKA_POWER_UP REG_FIELD_PREP(LVDS_A0A2_CLKA_POWER_MASK, 3)
|
||||
/*
|
||||
* Controls the A3 data pair, which contains the additional LSBs for 24 bit
|
||||
* mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
|
||||
* on.
|
||||
*/
|
||||
#define LVDS_A3_POWER_MASK (3 << 6)
|
||||
#define LVDS_A3_POWER_DOWN (0 << 6)
|
||||
#define LVDS_A3_POWER_UP (3 << 6)
|
||||
#define LVDS_A3_POWER_MASK REG_GENMASK(7, 6)
|
||||
#define LVDS_A3_POWER_DOWN REG_FIELD_PREP(LVDS_A3_POWER_MASK, 0)
|
||||
#define LVDS_A3_POWER_UP REG_FIELD_PREP(LVDS_A3_POWER_MASK, 3)
|
||||
/*
|
||||
* Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
|
||||
* is set.
|
||||
*/
|
||||
#define LVDS_CLKB_POWER_MASK (3 << 4)
|
||||
#define LVDS_CLKB_POWER_DOWN (0 << 4)
|
||||
#define LVDS_CLKB_POWER_UP (3 << 4)
|
||||
#define LVDS_CLKB_POWER_MASK REG_GENMASK(5, 4)
|
||||
#define LVDS_CLKB_POWER_DOWN REG_FIELD_PREP(LVDS_CLKB_POWER_MASK, 0)
|
||||
#define LVDS_CLKB_POWER_UP REG_FIELD_PREP(LVDS_CLKB_POWER_MASK, 3)
|
||||
/*
|
||||
* Controls the B0-B3 data pairs. This must be set to match the DPLL p2
|
||||
* setting for whether we are in dual-channel mode. The B3 pair will
|
||||
* additionally only be powered up when LVDS_A3_POWER_UP is set.
|
||||
*/
|
||||
#define LVDS_B0B3_POWER_MASK (3 << 2)
|
||||
#define LVDS_B0B3_POWER_DOWN (0 << 2)
|
||||
#define LVDS_B0B3_POWER_UP (3 << 2)
|
||||
#define LVDS_B0B3_POWER_MASK REG_GENMASK(3, 2)
|
||||
#define LVDS_B0B3_POWER_DOWN REG_FIELD_PREP(LVDS_B0B3_POWER_MASK, 0)
|
||||
#define LVDS_B0B3_POWER_UP REG_FIELD_PREP(LVDS_B0B3_POWER_MASK, 3)
|
||||
|
||||
/* Video Data Island Packet control */
|
||||
#define VIDEO_DIP_DATA _MMIO(0x61178)
|
||||
|
|
@ -6461,7 +6459,7 @@
|
|||
#define FDI_PLL_CTL_2 _MMIO(0xfe004)
|
||||
|
||||
#define PCH_LVDS _MMIO(0xe1180)
|
||||
#define LVDS_DETECTED (1 << 1)
|
||||
#define LVDS_DETECTED REG_BIT(1)
|
||||
|
||||
#define _PCH_DP_B 0xe4100
|
||||
#define PCH_DP_B _MMIO(_PCH_DP_B)
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $OpenBSD: kern_malloc.c,v 1.149 2023/11/29 11:47:15 claudio Exp $ */
|
||||
/* $OpenBSD: kern_malloc.c,v 1.151 2023/12/14 14:04:57 claudio Exp $ */
|
||||
/* $NetBSD: kern_malloc.c,v 1.15.4.2 1996/06/13 17:10:56 cgd Exp $ */
|
||||
|
||||
/*
|
||||
|
|
@ -83,19 +83,10 @@ struct vm_map *kmem_map = NULL;
|
|||
* config file.
|
||||
*/
|
||||
#ifndef NKMEMPAGES
|
||||
#define NKMEMPAGES 0
|
||||
#define NKMEMPAGES -1
|
||||
#endif
|
||||
u_int nkmempages = NKMEMPAGES;
|
||||
|
||||
/*
|
||||
* Defaults for upper-bounds for the kmem_map page count.
|
||||
* Can be overridden by kernel config options.
|
||||
*/
|
||||
#ifndef NKMEMPAGES_MAX
|
||||
#define NKMEMPAGES_MAX NKMEMPAGES_MAX_DEFAULT
|
||||
#endif
|
||||
u_int nkmempages_max = NKMEMPAGES_MAX;
|
||||
|
||||
struct mutex malloc_mtx = MUTEX_INITIALIZER(IPL_VM);
|
||||
struct kmembuckets bucket[MINBUCKET + 16];
|
||||
#ifdef KMEMSTATS
|
||||
|
|
@ -504,7 +495,7 @@ kmeminit_nkmempages(void)
|
|||
{
|
||||
u_int npages;
|
||||
|
||||
if (nkmempages != 0) {
|
||||
if (nkmempages != -1) {
|
||||
/*
|
||||
* It's already been set (by us being here before, or
|
||||
* by patching or kernel config options), bail out now.
|
||||
|
|
@ -515,16 +506,26 @@ kmeminit_nkmempages(void)
|
|||
/*
|
||||
* We use the following (simple) formula:
|
||||
*
|
||||
* - Starting point is physical memory / 4.
|
||||
* Up to 1G physmem use physical memory / 4,
|
||||
* above 1G add an extra 16MB per 1G of memory.
|
||||
*
|
||||
* - Clamp it down to nkmempages_max.
|
||||
*
|
||||
* - Round it up to nkmempages_min.
|
||||
* Clamp it down depending on VM_KERNEL_SPACE_SIZE
|
||||
* - up and including 512M -> 64MB
|
||||
* - between 512M and 1024M -> 128MB
|
||||
* - over 1024M clamping to VM_KERNEL_SPACE_SIZE / 4
|
||||
*/
|
||||
npages = physmem / 4;
|
||||
npages = MIN(physmem, atop(1024 * 1024 * 1024)) / 4;
|
||||
if (physmem > atop(1024 * 1024 * 1024))
|
||||
npages += (physmem - atop(1024 * 1024 * 1024)) / 64;
|
||||
|
||||
if (npages > nkmempages_max)
|
||||
npages = nkmempages_max;
|
||||
if (VM_KERNEL_SPACE_SIZE <= 512 * 1024 * 1024) {
|
||||
if (npages > atop(64 * 1024 * 1024))
|
||||
npages = atop(64 * 1024 * 1024);
|
||||
} else if (VM_KERNEL_SPACE_SIZE <= 1024 * 1024 * 1024) {
|
||||
if (npages > atop(128 * 1024 * 1024))
|
||||
npages = atop(128 * 1024 * 1024);
|
||||
} else if (npages > atop(VM_KERNEL_SPACE_SIZE) / 4)
|
||||
npages = atop(VM_KERNEL_SPACE_SIZE) / 4;
|
||||
|
||||
nkmempages = npages;
|
||||
}
|
||||
|
|
@ -573,7 +574,8 @@ kmeminit(void)
|
|||
bucket[indx].kb_highwat = 5 * bucket[indx].kb_elmpercl;
|
||||
}
|
||||
for (indx = 0; indx < M_LAST; indx++)
|
||||
kmemstats[indx].ks_limit = nkmempages * PAGE_SIZE * 6 / 10;
|
||||
kmemstats[indx].ks_limit =
|
||||
(long)nkmempages * PAGE_SIZE * 6 / 10;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $OpenBSD: in_pcb.h,v 1.143 2023/12/07 16:08:30 bluhm Exp $ */
|
||||
/* $OpenBSD: in_pcb.h,v 1.144 2023/12/15 00:24:56 bluhm Exp $ */
|
||||
/* $NetBSD: in_pcb.h,v 1.14 1996/02/13 23:42:00 christos Exp $ */
|
||||
|
||||
/*
|
||||
|
|
@ -107,14 +107,14 @@ struct inpcb {
|
|||
TAILQ_ENTRY(inpcb) inp_queue; /* [t] inet PCB queue */
|
||||
SIMPLEQ_ENTRY(inpcb) inp_notify; /* [y] notify or udp append */
|
||||
struct inpcbtable *inp_table; /* [I] inet queue/hash table */
|
||||
union inpaddru inp_faddru; /* Foreign address. */
|
||||
union inpaddru inp_laddru; /* Local address. */
|
||||
union inpaddru inp_faddru; /* [t] Foreign address. */
|
||||
union inpaddru inp_laddru; /* [t] Local address. */
|
||||
#define inp_faddr inp_faddru.iau_a4u.inaddr
|
||||
#define inp_faddr6 inp_faddru.iau_addr6
|
||||
#define inp_laddr inp_laddru.iau_a4u.inaddr
|
||||
#define inp_laddr6 inp_laddru.iau_addr6
|
||||
u_int16_t inp_fport; /* foreign port */
|
||||
u_int16_t inp_lport; /* local port */
|
||||
u_int16_t inp_fport; /* [t] foreign port */
|
||||
u_int16_t inp_lport; /* [t] local port */
|
||||
struct socket *inp_socket; /* [I] back pointer to socket */
|
||||
caddr_t inp_ppcb; /* pointer to per-protocol pcb */
|
||||
union { /* Route (notice increased size). */
|
||||
|
|
@ -159,7 +159,7 @@ struct inpcb {
|
|||
struct mbuf *(*inp_upcall)(void *, struct mbuf *,
|
||||
struct ip *, struct ip6_hdr *, void *, int);
|
||||
void *inp_upcall_arg;
|
||||
u_int inp_rtableid;
|
||||
u_int inp_rtableid; /* [t] */
|
||||
int inp_pipex; /* pipex indication */
|
||||
uint16_t inp_flowid;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $OpenBSD: ip_gre.c,v 1.86 2023/04/08 13:50:22 mvs Exp $ */
|
||||
/* $OpenBSD: ip_gre.c,v 1.87 2023/12/15 00:24:56 bluhm Exp $ */
|
||||
/* $NetBSD: ip_gre.c,v 1.9 1999/10/25 19:18:11 drochner Exp $ */
|
||||
|
||||
/*
|
||||
|
|
@ -85,7 +85,7 @@ gre_send(struct socket *so, struct mbuf *m, struct mbuf *nam,
|
|||
|
||||
if (inp->inp_pipex) {
|
||||
struct sockaddr_in *sin4;
|
||||
struct in_addr *ina_dst;
|
||||
const struct in_addr *ina_dst;
|
||||
|
||||
ina_dst = NULL;
|
||||
if ((so->so_state & SS_ISCONNECTED) != 0)
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $OpenBSD: raw_ip.c,v 1.152 2023/11/26 22:08:10 bluhm Exp $ */
|
||||
/* $OpenBSD: raw_ip.c,v 1.153 2023/12/15 00:24:56 bluhm Exp $ */
|
||||
/* $NetBSD: raw_ip.c,v 1.25 1996/02/18 18:58:33 christos Exp $ */
|
||||
|
||||
/*
|
||||
|
|
@ -545,7 +545,9 @@ rip_bind(struct socket *so, struct mbuf *nam, struct proc *p)
|
|||
ifa_ifwithaddr(sintosa(addr), inp->inp_rtableid)))
|
||||
return (EADDRNOTAVAIL);
|
||||
|
||||
mtx_enter(&rawcbtable.inpt_mtx);
|
||||
inp->inp_laddr = addr->sin_addr;
|
||||
mtx_leave(&rawcbtable.inpt_mtx);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
|
@ -562,7 +564,9 @@ rip_connect(struct socket *so, struct mbuf *nam)
|
|||
if ((error = in_nam2sin(nam, &addr)))
|
||||
return (error);
|
||||
|
||||
mtx_enter(&rawcbtable.inpt_mtx);
|
||||
inp->inp_faddr = addr->sin_addr;
|
||||
mtx_leave(&rawcbtable.inpt_mtx);
|
||||
soisconnected(so);
|
||||
|
||||
return (0);
|
||||
|
|
@ -579,7 +583,9 @@ rip_disconnect(struct socket *so)
|
|||
return (ENOTCONN);
|
||||
|
||||
soisdisconnected(so);
|
||||
mtx_enter(&rawcbtable.inpt_mtx);
|
||||
inp->inp_faddr.s_addr = INADDR_ANY;
|
||||
mtx_leave(&rawcbtable.inpt_mtx);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $OpenBSD: in6_src.c,v 1.89 2023/12/03 20:36:24 bluhm Exp $ */
|
||||
/* $OpenBSD: in6_src.c,v 1.90 2023/12/15 00:24:56 bluhm Exp $ */
|
||||
/* $KAME: in6_src.c,v 1.36 2001/02/06 04:08:17 itojun Exp $ */
|
||||
|
||||
/*
|
||||
|
|
@ -96,7 +96,7 @@ in6_pcbselsrc(const struct in6_addr **in6src, struct sockaddr_in6 *dstsock,
|
|||
{
|
||||
struct ip6_moptions *mopts = inp->inp_moptions6;
|
||||
struct route_in6 *ro = &inp->inp_route6;
|
||||
struct in6_addr *laddr = &inp->inp_laddr6;
|
||||
const struct in6_addr *laddr = &inp->inp_laddr6;
|
||||
u_int rtableid = inp->inp_rtableid;
|
||||
struct ifnet *ifp = NULL;
|
||||
struct sockaddr *ip6_source = NULL;
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $OpenBSD: raw_ip6.c,v 1.177 2023/12/03 20:36:24 bluhm Exp $ */
|
||||
/* $OpenBSD: raw_ip6.c,v 1.178 2023/12/15 00:24:56 bluhm Exp $ */
|
||||
/* $KAME: raw_ip6.c,v 1.69 2001/03/04 15:55:44 itojun Exp $ */
|
||||
|
||||
/*
|
||||
|
|
@ -674,7 +674,10 @@ rip6_bind(struct socket *so, struct mbuf *nam, struct proc *p)
|
|||
if ((error = in6_pcbaddrisavail(inp, addr, 0, p)))
|
||||
return (error);
|
||||
|
||||
mtx_enter(&rawin6pcbtable.inpt_mtx);
|
||||
inp->inp_laddr6 = addr->sin6_addr;
|
||||
mtx_leave(&rawin6pcbtable.inpt_mtx);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
|
@ -696,9 +699,12 @@ rip6_connect(struct socket *so, struct mbuf *nam)
|
|||
if (error)
|
||||
return (error);
|
||||
|
||||
mtx_enter(&rawin6pcbtable.inpt_mtx);
|
||||
inp->inp_laddr6 = *in6a;
|
||||
inp->inp_faddr6 = addr->sin6_addr;
|
||||
mtx_leave(&rawin6pcbtable.inpt_mtx);
|
||||
soisconnected(so);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
|
@ -712,8 +718,11 @@ rip6_disconnect(struct socket *so)
|
|||
if ((so->so_state & SS_ISCONNECTED) == 0)
|
||||
return (ENOTCONN);
|
||||
|
||||
inp->inp_faddr6 = in6addr_any;
|
||||
so->so_state &= ~SS_ISCONNECTED; /* XXX */
|
||||
mtx_enter(&rawin6pcbtable.inpt_mtx);
|
||||
inp->inp_faddr6 = in6addr_any;
|
||||
mtx_leave(&rawin6pcbtable.inpt_mtx);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue