sync with OpenBSD -current
This commit is contained in:
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61b0c3d2c1
commit
297ba4a59a
GPG key ID:
F42C07F07E2E35B7
20 changed files with 338 additions and 251 deletions
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@ -1,4 +1,4 @@
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/* $OpenBSD: vmm_machdep.c,v 1.21 2024/03/12 02:31:15 guenther Exp $ */
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/* $OpenBSD: vmm_machdep.c,v 1.22 2024/04/01 05:11:49 guenther Exp $ */
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/*
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* Copyright (c) 2014 Mike Larkin <mlarkin@openbsd.org>
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*
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@ -2329,7 +2329,7 @@ vcpu_reset_regs_vmx(struct vcpu *vcpu, struct vcpu_reg_state *vrs)
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uint32_t cr0, cr4;
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uint32_t pinbased, procbased, procbased2, exit, entry;
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uint32_t want1, want0;
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uint64_t ctrlval, cr3;
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uint64_t ctrlval, cr3, msr_misc_enable;
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uint16_t ctrl, vpid;
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struct vmx_msr_store *msr_store;
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@ -2723,24 +2723,26 @@ vcpu_reset_regs_vmx(struct vcpu *vcpu, struct vcpu_reg_state *vrs)
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vrs->vrs_crs[VCPU_REGS_CR0] = cr0;
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vrs->vrs_crs[VCPU_REGS_CR4] = cr4;
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msr_misc_enable = rdmsr(MSR_MISC_ENABLE);
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/*
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* Select host MSRs to be loaded on exit
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*/
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msr_store = (struct vmx_msr_store *)vcpu->vc_vmx_msr_exit_load_va;
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msr_store[0].vms_index = MSR_EFER;
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msr_store[0].vms_data = rdmsr(MSR_EFER);
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msr_store[1].vms_index = MSR_STAR;
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msr_store[1].vms_data = rdmsr(MSR_STAR);
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msr_store[2].vms_index = MSR_LSTAR;
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msr_store[2].vms_data = rdmsr(MSR_LSTAR);
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msr_store[3].vms_index = MSR_CSTAR;
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msr_store[3].vms_data = 0;
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msr_store[4].vms_index = MSR_SFMASK;
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msr_store[4].vms_data = rdmsr(MSR_SFMASK);
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msr_store[5].vms_index = MSR_KERNELGSBASE;
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msr_store[5].vms_data = rdmsr(MSR_KERNELGSBASE);
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msr_store[6].vms_index = MSR_MISC_ENABLE;
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msr_store[6].vms_data = rdmsr(MSR_MISC_ENABLE);
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msr_store[VCPU_HOST_REGS_EFER].vms_index = MSR_EFER;
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msr_store[VCPU_HOST_REGS_EFER].vms_data = rdmsr(MSR_EFER);
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msr_store[VCPU_HOST_REGS_STAR].vms_index = MSR_STAR;
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msr_store[VCPU_HOST_REGS_STAR].vms_data = rdmsr(MSR_STAR);
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msr_store[VCPU_HOST_REGS_LSTAR].vms_index = MSR_LSTAR;
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msr_store[VCPU_HOST_REGS_LSTAR].vms_data = rdmsr(MSR_LSTAR);
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msr_store[VCPU_HOST_REGS_CSTAR].vms_index = MSR_CSTAR;
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msr_store[VCPU_HOST_REGS_CSTAR].vms_data = 0;
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msr_store[VCPU_HOST_REGS_SFMASK].vms_index = MSR_SFMASK;
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msr_store[VCPU_HOST_REGS_SFMASK].vms_data = rdmsr(MSR_SFMASK);
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msr_store[VCPU_HOST_REGS_KGSBASE].vms_index = MSR_KERNELGSBASE;
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msr_store[VCPU_HOST_REGS_KGSBASE].vms_data = 0;
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msr_store[VCPU_HOST_REGS_MISC_ENABLE].vms_index = MSR_MISC_ENABLE;
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msr_store[VCPU_HOST_REGS_MISC_ENABLE].vms_data = msr_misc_enable;
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/*
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* Select guest MSRs to be loaded on entry / saved on exit
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@ -2759,7 +2761,7 @@ vcpu_reset_regs_vmx(struct vcpu *vcpu, struct vcpu_reg_state *vrs)
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* Initialize MSR_MISC_ENABLE as it can't be read and populated from vmd
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* and some of the content is based on the host.
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*/
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msr_store[VCPU_REGS_MISC_ENABLE].vms_data = rdmsr(MSR_MISC_ENABLE);
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msr_store[VCPU_REGS_MISC_ENABLE].vms_data = msr_misc_enable;
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msr_store[VCPU_REGS_MISC_ENABLE].vms_data &=
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~(MISC_ENABLE_TCC | MISC_ENABLE_PERF_MON_AVAILABLE |
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MISC_ENABLE_EIST_ENABLED | MISC_ENABLE_ENABLE_MONITOR_FSM |
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@ -2768,24 +2770,26 @@ vcpu_reset_regs_vmx(struct vcpu *vcpu, struct vcpu_reg_state *vrs)
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MISC_ENABLE_BTS_UNAVAILABLE | MISC_ENABLE_PEBS_UNAVAILABLE;
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/*
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* Currently we have the same count of entry/exit MSRs loads/stores
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* but this is not an architectural requirement.
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* Currently we use the same memory for guest MSRs (entry-load and
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* exit-store) so they have the same count. We exit-load the same
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* host MSRs, so same count but different memory. Those are just
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* our current choices, not architectural requirements.
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*/
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if (vmwrite(VMCS_EXIT_MSR_STORE_COUNT, VMX_NUM_MSR_STORE)) {
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if (vmwrite(VMCS_EXIT_MSR_STORE_COUNT, VCPU_REGS_NMSRS)) {
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DPRINTF("%s: error setting guest MSR exit store count\n",
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__func__);
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ret = EINVAL;
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goto exit;
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}
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if (vmwrite(VMCS_EXIT_MSR_LOAD_COUNT, VMX_NUM_MSR_STORE)) {
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if (vmwrite(VMCS_EXIT_MSR_LOAD_COUNT, VCPU_HOST_REGS_NMSRS)) {
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DPRINTF("%s: error setting guest MSR exit load count\n",
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__func__);
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ret = EINVAL;
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goto exit;
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}
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if (vmwrite(VMCS_ENTRY_MSR_LOAD_COUNT, VMX_NUM_MSR_STORE)) {
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if (vmwrite(VMCS_ENTRY_MSR_LOAD_COUNT, VCPU_REGS_NMSRS)) {
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DPRINTF("%s: error setting guest MSR entry load count\n",
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__func__);
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ret = EINVAL;
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@ -2974,6 +2978,7 @@ vcpu_init_vmx(struct vcpu *vcpu)
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goto exit;
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}
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#if 0 /* XXX currently use msr_exit_save for msr_entry_load too */
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/* Allocate MSR entry load area VA */
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vcpu->vc_vmx_msr_entry_load_va = (vaddr_t)km_alloc(PAGE_SIZE, &kv_page,
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&kp_zero, &kd_waitok);
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@ -2989,6 +2994,7 @@ vcpu_init_vmx(struct vcpu *vcpu)
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ret = ENOMEM;
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goto exit;
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}
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#endif
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vmcs = (struct vmcs *)vcpu->vc_control_va;
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vmcs->vmcs_revision = curcpu()->ci_vmm_cap.vcc_vmx.vmx_vmxon_revision;
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@ -3308,11 +3314,13 @@ vcpu_deinit_vmx(struct vcpu *vcpu)
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PAGE_SIZE, &kv_page, &kp_zero);
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vcpu->vc_vmx_msr_exit_load_va = 0;
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}
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#if 0
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if (vcpu->vc_vmx_msr_entry_load_va) {
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km_free((void *)vcpu->vc_vmx_msr_entry_load_va,
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PAGE_SIZE, &kv_page, &kp_zero);
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vcpu->vc_vmx_msr_entry_load_va = 0;
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}
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#endif
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if (vcpu->vc_vmx_vpid_enabled)
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vmm_free_vpid(vcpu->vc_vpid);
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@ -3954,8 +3962,9 @@ vcpu_run_vmx(struct vcpu *vcpu, struct vm_run_params *vrp)
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int ret = 0, exitinfo;
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struct region_descriptor gdt;
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struct cpu_info *ci = NULL;
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uint64_t exit_reason, cr3, insn_error;
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uint64_t exit_reason, cr3, msr, insn_error;
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struct schedstate_percpu *spc;
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struct vmx_msr_store *msr_store;
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struct vmx_invvpid_descriptor vid;
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uint64_t eii, procbased, int_st;
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uint16_t irq;
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@ -4091,6 +4100,7 @@ vcpu_run_vmx(struct vcpu *vcpu, struct vm_run_params *vrp)
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}
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}
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msr_store = (struct vmx_msr_store *)vcpu->vc_vmx_msr_exit_load_va;
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while (ret == 0) {
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#ifdef VMM_DEBUG
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paddr_t pa = 0ULL;
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(uint64_t)ci->ci_tss);
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return (EINVAL);
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}
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/* Host GS.base (aka curcpu) */
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if (vmwrite(VMCS_HOST_IA32_GS_BASE, (uint64_t)ci)) {
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printf("%s: vmwrite(0x%04X, 0x%llx)\n",
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__func__, VMCS_HOST_IA32_GS_BASE,
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(uint64_t)ci);
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return (EINVAL);
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}
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/* Host FS.base */
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msr = rdmsr(MSR_FSBASE);
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if (vmwrite(VMCS_HOST_IA32_FS_BASE, msr)) {
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printf("%s: vmwrite(0x%04X, 0x%llx)\n",
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__func__, VMCS_HOST_IA32_FS_BASE, msr);
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return (EINVAL);
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}
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/* Host KernelGS.base (userspace GS.base here) */
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msr_store[VCPU_HOST_REGS_KGSBASE].vms_data =
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rdmsr(MSR_KERNELGSBASE);
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}
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/* Inject event if present */
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msr_store = (struct vmx_msr_store *)vcpu->vc_vmx_msr_exit_save_va;
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for (i = 0; i < VMX_NUM_MSR_STORE; i++) {
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for (i = 0; i < VCPU_REGS_NMSRS; i++) {
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DPRINTF(" MSR %d @ %p : 0x%08llx (%s), "
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"value=0x%016llx ",
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i, &msr_store[i], msr_store[i].vms_index,
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@ -1,4 +1,4 @@
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/* $OpenBSD: vmm_support.S,v 1.26 2024/03/17 05:49:41 guenther Exp $ */
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/* $OpenBSD: vmm_support.S,v 1.27 2024/04/01 05:11:49 guenther Exp $ */
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/*
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* Copyright (c) 2014 Mike Larkin <mlarkin@openbsd.org>
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*
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@ -177,59 +177,6 @@ ENTRY(vmx_enter_guest)
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vmwrite %rax, %rdi /* Host RIP */
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skip_init:
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/*
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* XXX use msr list here for restore instead of all this
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* stack jiggery-pokery
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*/
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pushfq
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popq %rax
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andq $(~PSL_I), %rax
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pushq %rax
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/*
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* Save (possibly) lazy-switched selectors
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*/
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movw %es, %ax
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pushw %ax
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movw %ds, %ax
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pushw %ax
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movw %ss, %ax
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pushw %ax
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movq $MSR_FSBASE, %rcx
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rdmsr
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pushq %rax
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pushq %rdx
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pushw %fs
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movq $MSR_GSBASE, %rcx
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rdmsr
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pushq %rax
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pushq %rdx
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pushw %gs
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movq $MSR_KERNELGSBASE, %rcx
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rdmsr
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pushq %rax
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pushq %rdx
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/*
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* Save various MSRs
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*/
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movq $MSR_STAR, %rcx
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rdmsr
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pushq %rax
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pushq %rdx
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movq $MSR_LSTAR, %rcx
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rdmsr
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pushq %rax
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pushq %rdx
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movq $MSR_SFMASK, %rcx
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rdmsr
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pushq %rax
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pushq %rdx
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RETGUARD_PUSH(r11)
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/* Preserve callee-preserved registers as per AMD64 ABI */
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RETGUARD_POP(r11)
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/*
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* Restore saved MSRs
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*/
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popq %rdx
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popq %rax
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movq $MSR_SFMASK, %rcx
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wrmsr
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/* make sure guest doesn't bleed into host */
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xorl %edx, %edx
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xorl %eax, %eax
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movq $MSR_CSTAR, %rcx
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wrmsr
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popq %rdx
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popq %rax
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movq $MSR_LSTAR, %rcx
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wrmsr
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popq %rdx
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popq %rax
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movq $MSR_STAR, %rcx
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wrmsr
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/*
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* popw %gs will reset gsbase to 0, so preserve it
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* first. This is to accommodate possibly lazy-switched
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* selectors from above
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*/
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popq %rdx
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popq %rax
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movq $MSR_KERNELGSBASE, %rcx
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wrmsr
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popw %gs
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popq %rdx
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popq %rax
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movq $MSR_GSBASE, %rcx
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wrmsr
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popw %fs
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popq %rdx
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popq %rax
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movq $MSR_FSBASE, %rcx
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wrmsr
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popw %ax
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movw %ax, %ss
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popw %ax
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movw %ax, %ds
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popw %ax
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movw %ax, %es
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popfq
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movq %rdi, %rax
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RETGUARD_CHECK(vmx_enter_guest, r11)
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ret
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@ -1,4 +1,4 @@
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/* $OpenBSD: vmmvar.h,v 1.98 2024/01/20 20:11:24 mlarkin Exp $ */
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/* $OpenBSD: vmmvar.h,v 1.99 2024/04/01 05:11:49 guenther Exp $ */
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/*
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* Copyright (c) 2014 Mike Larkin <mlarkin@openbsd.org>
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*
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@ -435,6 +435,15 @@ struct vcpu_reg_state {
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struct vcpu_segment_info vrs_idtr;
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};
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#define VCPU_HOST_REGS_EFER 0
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#define VCPU_HOST_REGS_STAR 1
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#define VCPU_HOST_REGS_LSTAR 2
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#define VCPU_HOST_REGS_CSTAR 3
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#define VCPU_HOST_REGS_SFMASK 4
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#define VCPU_HOST_REGS_KGSBASE 5
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#define VCPU_HOST_REGS_MISC_ENABLE 6
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#define VCPU_HOST_REGS_NMSRS (VCPU_HOST_REGS_MISC_ENABLE + 1)
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/*
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* struct vm_exit
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*
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@ -617,8 +626,6 @@ struct vm_mprotect_ept_params {
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#define VMX_FAIL_LAUNCH_INVALID_VMCS 2
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#define VMX_FAIL_LAUNCH_VALID_VMCS 3
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#define VMX_NUM_MSR_STORE 7
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/* MSR bitmap manipulation macros */
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#define VMX_MSRIDX(m) ((m) / 8)
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#define VMX_MSRBIT(m) (1 << (m) % 8)
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@ -894,8 +901,10 @@ struct vcpu {
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paddr_t vc_vmx_msr_exit_save_pa;
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vaddr_t vc_vmx_msr_exit_load_va;
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paddr_t vc_vmx_msr_exit_load_pa;
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#if 0 /* XXX currently use msr_exit_save for msr_entry_load too */
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vaddr_t vc_vmx_msr_entry_load_va;
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paddr_t vc_vmx_msr_entry_load_pa;
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#endif
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uint8_t vc_vmx_vpid_enabled;
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uint64_t vc_vmx_cr0_fixed1;
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uint64_t vc_vmx_cr0_fixed0;
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