sync with OpenBSD -current
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F42C07F07E2E35B7
1651 changed files with 283292 additions and 68089 deletions
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@ -5,6 +5,7 @@
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*/
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#include "i915_drv.h"
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#include "i915_reg.h"
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#include "intel_de.h"
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#include "intel_display_types.h"
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#include "intel_vrr.h"
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@ -77,10 +78,10 @@ static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_stat
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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struct drm_i915_private *i915 = to_i915(crtc->base.dev);
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/* The hw imposes the extra scanline before frame start */
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if (DISPLAY_VER(i915) >= 13)
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return crtc_state->vrr.guardband + crtc_state->framestart_delay + 1;
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return crtc_state->vrr.guardband;
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else
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/* The hw imposes the extra scanline before frame start */
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return crtc_state->vrr.pipeline_full + crtc_state->framestart_delay + 1;
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}
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@ -113,9 +114,6 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
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if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
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return;
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if (!crtc_state->uapi.vrr_enabled)
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return;
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vmin = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000,
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adjusted_mode->crtc_htotal * info->monitor_range.max_vfreq);
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vmax = adjusted_mode->crtc_clock * 1000 /
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@ -134,7 +132,6 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
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*/
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crtc_state->vrr.vmin = vmin - 1;
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crtc_state->vrr.vmax = vmax;
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crtc_state->vrr.enable = true;
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crtc_state->vrr.flipline = crtc_state->vrr.vmin + 1;
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@ -143,57 +140,55 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
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* is deprecated.
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*/
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if (DISPLAY_VER(i915) >= 13) {
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/*
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* FIXME: Subtract Window2 delay from below value.
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*
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* Window2 specifies time required to program DSB (Window2) in
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* number of scan lines. Assuming 0 for no DSB.
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*/
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crtc_state->vrr.guardband =
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crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay;
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crtc_state->vrr.vmin + 1 - adjusted_mode->crtc_vblank_start;
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} else {
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/*
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* FIXME: s/4/framestart_delay/ to get consistent
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* earliest/latest points for register latching regardless
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* of the framestart_delay used?
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*
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* FIXME: this really needs the extra scanline to provide consistent
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* behaviour for all framestart_delay values. Otherwise with
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* framestart_delay==4 we will end up extending the min vblank by
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* one extra line.
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*/
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crtc_state->vrr.pipeline_full =
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min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay - 4 - 1);
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min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start -
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crtc_state->framestart_delay - 1);
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}
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crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
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if (crtc_state->uapi.vrr_enabled) {
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crtc_state->vrr.enable = true;
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crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
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}
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}
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void intel_vrr_enable(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state)
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static u32 trans_vrr_ctl(const struct intel_crtc_state *crtc_state)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
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u32 trans_vrr_ctl;
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struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
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if (!crtc_state->vrr.enable)
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return;
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if (DISPLAY_VER(dev_priv) >= 13)
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trans_vrr_ctl = VRR_CTL_VRR_ENABLE |
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VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN |
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if (DISPLAY_VER(i915) >= 13)
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return VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN |
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XELPD_VRR_CTL_VRR_GUARDBAND(crtc_state->vrr.guardband);
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else
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trans_vrr_ctl = VRR_CTL_VRR_ENABLE |
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VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN |
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return VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN |
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VRR_CTL_PIPELINE_FULL(crtc_state->vrr.pipeline_full) |
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VRR_CTL_PIPELINE_FULL_OVERRIDE;
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}
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void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
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{
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struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
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enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
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/*
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* TRANS_SET_CONTEXT_LATENCY with VRR enabled
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* requires this chicken bit on ADL/DG2.
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*/
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if (DISPLAY_VER(dev_priv) == 13)
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intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder),
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0, PIPE_VBLANK_WITH_DELAY);
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if (!crtc_state->vrr.flipline) {
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intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), 0);
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return;
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}
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intel_de_write(dev_priv, TRANS_VRR_VMIN(cpu_transcoder), crtc_state->vrr.vmin - 1);
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intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), crtc_state->vrr.vmax - 1);
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intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), trans_vrr_ctl);
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intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), trans_vrr_ctl(crtc_state));
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intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder), crtc_state->vrr.flipline - 1);
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intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN);
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}
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void intel_vrr_send_push(const struct intel_crtc_state *crtc_state)
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@ -221,6 +216,19 @@ bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state)
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return intel_de_read(dev_priv, TRANS_PUSH(cpu_transcoder)) & TRANS_PUSH_SEND;
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}
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void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
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{
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struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
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enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
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if (!crtc_state->vrr.enable)
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return;
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intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN);
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intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder),
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VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
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}
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void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
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{
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struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
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@ -230,21 +238,22 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
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if (!old_crtc_state->vrr.enable)
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return;
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intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), 0);
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intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder),
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trans_vrr_ctl(old_crtc_state));
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intel_de_wait_for_clear(dev_priv, TRANS_VRR_STATUS(cpu_transcoder),
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VRR_STATUS_VRR_EN_LIVE, 1000);
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intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), 0);
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}
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void intel_vrr_get_config(struct intel_crtc *crtc,
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struct intel_crtc_state *crtc_state)
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void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
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{
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
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enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
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u32 trans_vrr_ctl;
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trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(cpu_transcoder));
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crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE;
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if (!crtc_state->vrr.enable)
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return;
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if (DISPLAY_VER(dev_priv) >= 13)
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crtc_state->vrr.guardband =
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if (trans_vrr_ctl & VRR_CTL_PIPELINE_FULL_OVERRIDE)
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crtc_state->vrr.pipeline_full =
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REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl);
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if (trans_vrr_ctl & VRR_CTL_FLIP_LINE_EN)
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crtc_state->vrr.flipline = intel_de_read(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder)) + 1;
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crtc_state->vrr.vmax = intel_de_read(dev_priv, TRANS_VRR_VMAX(cpu_transcoder)) + 1;
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crtc_state->vrr.vmin = intel_de_read(dev_priv, TRANS_VRR_VMIN(cpu_transcoder)) + 1;
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crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
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if (trans_vrr_ctl & VRR_CTL_FLIP_LINE_EN) {
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crtc_state->vrr.flipline = intel_de_read(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder)) + 1;
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crtc_state->vrr.vmax = intel_de_read(dev_priv, TRANS_VRR_VMAX(cpu_transcoder)) + 1;
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crtc_state->vrr.vmin = intel_de_read(dev_priv, TRANS_VRR_VMIN(cpu_transcoder)) + 1;
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}
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if (crtc_state->vrr.enable)
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crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
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}
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