sync with OpenBSD -current
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F42C07F07E2E35B7
1651 changed files with 283292 additions and 68089 deletions
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@ -38,6 +38,11 @@
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#define mmIH_CHICKEN_ALDEBARAN 0x18d
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#define mmIH_CHICKEN_ALDEBARAN_BASE_IDX 0
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#define mmIH_RETRY_INT_CAM_CNTL_ALDEBARAN 0x00ea
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#define mmIH_RETRY_INT_CAM_CNTL_ALDEBARAN_BASE_IDX 0
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#define IH_RETRY_INT_CAM_CNTL_ALDEBARAN__ENABLE__SHIFT 0x10
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#define IH_RETRY_INT_CAM_CNTL_ALDEBARAN__ENABLE_MASK 0x00010000L
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static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev);
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/**
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@ -251,36 +256,14 @@ static int vega20_ih_enable_ring(struct amdgpu_device *adev,
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return 0;
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}
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/**
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* vega20_ih_reroute_ih - reroute VMC/UTCL2 ih to an ih ring
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*
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* @adev: amdgpu_device pointer
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*
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* Reroute VMC and UMC interrupts on primary ih ring to
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* ih ring 1 so they won't lose when bunches of page faults
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* interrupts overwhelms the interrupt handler(VEGA20)
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*/
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static void vega20_ih_reroute_ih(struct amdgpu_device *adev)
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static uint32_t vega20_setup_retry_doorbell(u32 doorbell_index)
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{
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uint32_t tmp;
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u32 val = 0;
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/* vega20 ih reroute will go through psp this
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* function is used for newer asics starting arcturus
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*/
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if (adev->asic_type >= CHIP_ARCTURUS) {
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/* Reroute to IH ring 1 for VMC */
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WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x12);
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tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA);
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tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
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tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
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WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp);
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val = REG_SET_FIELD(val, IH_DOORBELL_RPTR, OFFSET, doorbell_index);
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val = REG_SET_FIELD(val, IH_DOORBELL_RPTR, ENABLE, 1);
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/* Reroute IH ring 1 for UTCL2 */
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WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x1B);
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tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA);
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tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
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WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp);
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}
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return val;
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}
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/**
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@ -308,7 +291,7 @@ static int vega20_ih_irq_init(struct amdgpu_device *adev)
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adev->nbio.funcs->ih_control(adev);
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if (adev->asic_type == CHIP_ARCTURUS &&
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if ((adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 2, 1)) &&
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adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
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ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN);
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if (adev->irq.ih.use_bus_addr) {
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@ -321,7 +304,8 @@ static int vega20_ih_irq_init(struct amdgpu_device *adev)
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/* psp firmware won't program IH_CHICKEN for aldebaran
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* driver needs to program it properly according to
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* MC_SPACE type in IH_RB_CNTL */
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if (adev->asic_type == CHIP_ALDEBARAN) {
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if ((adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 4, 0)) ||
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(adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 4, 2))) {
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ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_ALDEBARAN);
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if (adev->irq.ih.use_bus_addr) {
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ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN,
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@ -332,8 +316,6 @@ static int vega20_ih_irq_init(struct amdgpu_device *adev)
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for (i = 0; i < ARRAY_SIZE(ih); i++) {
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if (ih[i]->ring_size) {
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if (i == 1)
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vega20_ih_reroute_ih(adev);
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ret = vega20_ih_enable_ring(adev, ih[i]);
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if (ret)
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return ret;
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@ -346,6 +328,21 @@ static int vega20_ih_irq_init(struct amdgpu_device *adev)
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pci_set_master(adev->pdev);
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/* Allocate the doorbell for IH Retry CAM */
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adev->irq.retry_cam_doorbell_index = (adev->doorbell_index.ih + 3) << 1;
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WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RETRY_CAM,
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vega20_setup_retry_doorbell(adev->irq.retry_cam_doorbell_index));
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/* Enable IH Retry CAM */
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if (adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 4, 0) ||
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adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 4, 2))
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WREG32_FIELD15(OSSSYS, 0, IH_RETRY_INT_CAM_CNTL_ALDEBARAN,
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ENABLE, 1);
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else
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WREG32_FIELD15(OSSSYS, 0, IH_RETRY_INT_CAM_CNTL, ENABLE, 1);
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adev->irq.retry_cam_enabled = true;
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/* enable interrupts */
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ret = vega20_ih_toggle_interrupts(adev, true);
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if (ret)
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@ -503,7 +500,8 @@ static int vega20_ih_self_irq(struct amdgpu_device *adev,
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case 2:
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schedule_work(&adev->irq.ih2_work);
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break;
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default: break;
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default:
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break;
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}
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return 0;
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}
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@ -530,6 +528,7 @@ static int vega20_ih_early_init(void *handle)
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static int vega20_ih_sw_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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bool use_bus_addr = true;
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int r;
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r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0,
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@ -537,31 +536,37 @@ static int vega20_ih_sw_init(void *handle)
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if (r)
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return r;
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r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true);
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if ((adev->flags & AMD_IS_APU) &&
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(adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 4, 2)))
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use_bus_addr = false;
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r = amdgpu_ih_ring_init(adev, &adev->irq.ih, IH_RING_SIZE, use_bus_addr);
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if (r)
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return r;
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adev->irq.ih.use_doorbell = true;
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adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
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r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true);
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r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, use_bus_addr);
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if (r)
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return r;
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adev->irq.ih1.use_doorbell = true;
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adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1;
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r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true);
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if (r)
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return r;
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if (adev->ip_versions[OSSSYS_HWIP][0] != IP_VERSION(4, 4, 2)) {
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r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true);
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if (r)
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return r;
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adev->irq.ih2.use_doorbell = true;
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adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1;
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adev->irq.ih2.use_doorbell = true;
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adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1;
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}
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/* initialize ih control registers offset */
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vega20_ih_init_register_offset(adev);
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r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true);
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r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, IH_SW_RING_SIZE, use_bus_addr);
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if (r)
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return r;
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@ -706,8 +711,7 @@ static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev)
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adev->irq.ih_funcs = &vega20_ih_funcs;
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}
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const struct amdgpu_ip_block_version vega20_ih_ip_block =
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{
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const struct amdgpu_ip_block_version vega20_ih_ip_block = {
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.type = AMD_IP_BLOCK_TYPE_IH,
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.major = 4,
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.minor = 2,
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