sync with OpenBSD -current
This commit is contained in:
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ee68147dcd
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1cefe29c7e
GPG key ID:
F42C07F07E2E35B7
1651 changed files with 283292 additions and 68089 deletions
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@ -153,6 +153,24 @@ static const struct amdgpu_video_codecs rn_video_codecs_decode =
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.codec_array = rn_video_codecs_decode_array,
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};
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static const struct amdgpu_video_codec_info vcn_4_0_3_video_codecs_decode_array[] = {
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{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
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{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
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{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
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{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
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{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
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};
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static const struct amdgpu_video_codecs vcn_4_0_3_video_codecs_decode = {
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.codec_count = ARRAY_SIZE(vcn_4_0_3_video_codecs_decode_array),
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.codec_array = vcn_4_0_3_video_codecs_decode_array,
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};
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static const struct amdgpu_video_codecs vcn_4_0_3_video_codecs_encode = {
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.codec_count = 0,
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.codec_array = NULL,
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};
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static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode,
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const struct amdgpu_video_codecs **codecs)
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{
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@ -185,53 +203,18 @@ static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode,
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else
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*codecs = &rn_video_codecs_decode;
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return 0;
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case IP_VERSION(4, 0, 3):
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if (encode)
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*codecs = &vcn_4_0_3_video_codecs_encode;
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else
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*codecs = &vcn_4_0_3_video_codecs_decode;
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return 0;
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default:
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return -EINVAL;
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}
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}
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}
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/*
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* Indirect registers accessor
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*/
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static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
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{
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unsigned long address, data;
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address = adev->nbio.funcs->get_pcie_index_offset(adev);
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data = adev->nbio.funcs->get_pcie_data_offset(adev);
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return amdgpu_device_indirect_rreg(adev, address, data, reg);
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}
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static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
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{
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unsigned long address, data;
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address = adev->nbio.funcs->get_pcie_index_offset(adev);
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data = adev->nbio.funcs->get_pcie_data_offset(adev);
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amdgpu_device_indirect_wreg(adev, address, data, reg, v);
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}
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static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
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{
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unsigned long address, data;
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address = adev->nbio.funcs->get_pcie_index_offset(adev);
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data = adev->nbio.funcs->get_pcie_data_offset(adev);
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return amdgpu_device_indirect_rreg64(adev, address, data, reg);
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}
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static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
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{
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unsigned long address, data;
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address = adev->nbio.funcs->get_pcie_index_offset(adev);
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data = adev->nbio.funcs->get_pcie_data_offset(adev);
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amdgpu_device_indirect_wreg64(adev, address, data, reg, v);
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}
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static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
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{
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unsigned long flags, address, data;
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@ -342,7 +325,8 @@ static u32 soc15_get_xclk(struct amdgpu_device *adev)
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u32 reference_clock = adev->clock.spll.reference_freq;
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if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 0) ||
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adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 1))
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adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 1) ||
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adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 6))
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return 10000;
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if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 0) ||
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adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 1))
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@ -353,7 +337,7 @@ static u32 soc15_get_xclk(struct amdgpu_device *adev)
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void soc15_grbm_select(struct amdgpu_device *adev,
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u32 me, u32 pipe, u32 queue, u32 vmid)
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u32 me, u32 pipe, u32 queue, u32 vmid, int xcc_id)
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{
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u32 grbm_gfx_cntl = 0;
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grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
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@ -361,12 +345,7 @@ void soc15_grbm_select(struct amdgpu_device *adev,
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grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
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grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
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WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
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}
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static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
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{
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/* todo */
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WREG32_SOC15_RLC_SHADOW(GC, xcc_id, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
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}
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static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
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@ -405,12 +384,12 @@ static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_n
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mutex_lock(&adev->grbm_idx_mutex);
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if (se_num != 0xffffffff || sh_num != 0xffffffff)
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amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
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amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0);
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val = RREG32(reg_offset);
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if (se_num != 0xffffffff || sh_num != 0xffffffff)
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amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
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amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
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mutex_unlock(&adev->grbm_idx_mutex);
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return val;
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}
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@ -574,6 +553,17 @@ soc15_asic_reset_method(struct amdgpu_device *adev)
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if (connected_to_cpu)
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return AMD_RESET_METHOD_MODE2;
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break;
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case IP_VERSION(13, 0, 6):
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/* Use gpu_recovery param to target a reset method.
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* Enable triggering of GPU reset only if specified
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* by module parameter.
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*/
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if (amdgpu_gpu_recovery == 4 || amdgpu_gpu_recovery == 5)
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return AMD_RESET_METHOD_MODE2;
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else if (!(adev->flags & AMD_IS_APU))
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return AMD_RESET_METHOD_MODE1;
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else
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return AMD_RESET_METHOD_MODE2;
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default:
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break;
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}
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@ -651,24 +641,6 @@ static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk
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return 0;
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}
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static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
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{
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if (pci_is_root_bus(adev->pdev->bus))
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return;
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if (amdgpu_pcie_gen2 == 0)
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return;
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if (adev->flags & AMD_IS_APU)
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return;
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if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
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CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
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return;
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/* todo */
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}
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static void soc15_program_aspm(struct amdgpu_device *adev)
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{
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if (!amdgpu_device_should_use_aspm(adev))
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@ -679,13 +651,6 @@ static void soc15_program_aspm(struct amdgpu_device *adev)
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adev->nbio.funcs->program_aspm(adev);
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}
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static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
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bool enable)
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{
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adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
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adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
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}
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const struct amdgpu_ip_block_version vega10_common_ip_block =
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{
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.type = AMD_IP_BLOCK_TYPE_COMMON,
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@ -695,11 +660,6 @@ const struct amdgpu_ip_block_version vega10_common_ip_block =
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.funcs = &soc15_common_ip_funcs,
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};
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static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
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{
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return adev->nbio.funcs->get_rev_id(adev);
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}
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static void soc15_reg_base_init(struct amdgpu_device *adev)
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{
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/* Set IP register base before any HW register access */
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@ -888,7 +848,6 @@ static const struct amdgpu_asic_funcs soc15_asic_funcs =
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.read_register = &soc15_read_register,
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.reset = &soc15_asic_reset,
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.reset_method = &soc15_asic_reset_method,
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.set_vga_state = &soc15_vga_set_state,
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.get_xclk = &soc15_get_xclk,
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.set_uvd_clocks = &soc15_set_uvd_clocks,
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.set_vce_clocks = &soc15_set_vce_clocks,
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@ -910,7 +869,6 @@ static const struct amdgpu_asic_funcs vega20_asic_funcs =
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.read_register = &soc15_read_register,
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.reset = &soc15_asic_reset,
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.reset_method = &soc15_asic_reset_method,
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.set_vga_state = &soc15_vga_set_state,
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.get_xclk = &soc15_get_xclk,
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.set_uvd_clocks = &soc15_set_uvd_clocks,
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.set_vce_clocks = &soc15_set_vce_clocks,
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@ -925,6 +883,28 @@ static const struct amdgpu_asic_funcs vega20_asic_funcs =
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.query_video_codecs = &soc15_query_video_codecs,
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};
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static const struct amdgpu_asic_funcs aqua_vanjaram_asic_funcs =
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{
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.read_disabled_bios = &soc15_read_disabled_bios,
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.read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
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.read_register = &soc15_read_register,
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.reset = &soc15_asic_reset,
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.reset_method = &soc15_asic_reset_method,
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.get_xclk = &soc15_get_xclk,
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.set_uvd_clocks = &soc15_set_uvd_clocks,
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.set_vce_clocks = &soc15_set_vce_clocks,
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.get_config_memsize = &soc15_get_config_memsize,
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.need_full_reset = &soc15_need_full_reset,
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.init_doorbell_index = &aqua_vanjaram_doorbell_index_init,
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.get_pcie_usage = &amdgpu_nbio_get_pcie_usage,
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.need_reset_on_init = &soc15_need_reset_on_init,
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.get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count,
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.supports_baco = &soc15_supports_baco,
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.pre_asic_init = &soc15_pre_asic_init,
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.query_video_codecs = &soc15_query_video_codecs,
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.encode_ext_smn_addressing = &aqua_vanjaram_encode_ext_smn_addressing,
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};
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static int soc15_common_early_init(void *handle)
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{
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#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
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@ -936,10 +916,12 @@ static int soc15_common_early_init(void *handle)
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}
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adev->smc_rreg = NULL;
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adev->smc_wreg = NULL;
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adev->pcie_rreg = &soc15_pcie_rreg;
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adev->pcie_wreg = &soc15_pcie_wreg;
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adev->pcie_rreg64 = &soc15_pcie_rreg64;
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adev->pcie_wreg64 = &soc15_pcie_wreg64;
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adev->pcie_rreg = &amdgpu_device_indirect_rreg;
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adev->pcie_wreg = &amdgpu_device_indirect_wreg;
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adev->pcie_rreg_ext = &amdgpu_device_indirect_rreg_ext;
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adev->pcie_wreg_ext = &amdgpu_device_indirect_wreg_ext;
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adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64;
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adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64;
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adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
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adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
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adev->didt_rreg = &soc15_didt_rreg;
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@ -949,7 +931,7 @@ static int soc15_common_early_init(void *handle)
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adev->se_cac_rreg = &soc15_se_cac_rreg;
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adev->se_cac_wreg = &soc15_se_cac_wreg;
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adev->rev_id = soc15_get_rev_id(adev);
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adev->rev_id = amdgpu_device_get_rev_id(adev);
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adev->external_rev_id = 0xFF;
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/* TODO: split the GC and PG flags based on the relevant IP version for which
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* they are relevant.
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@ -1165,6 +1147,20 @@ static int soc15_common_early_init(void *handle)
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adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG;
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adev->external_rev_id = adev->rev_id + 0x3c;
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break;
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case IP_VERSION(9, 4, 3):
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adev->asic_funcs = &aqua_vanjaram_asic_funcs;
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adev->cg_flags =
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AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_CGCG |
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AMD_CG_SUPPORT_GFX_CGLS | AMD_CG_SUPPORT_SDMA_MGCG |
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AMD_CG_SUPPORT_GFX_FGCG | AMD_CG_SUPPORT_REPEATER_FGCG |
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AMD_CG_SUPPORT_VCN_MGCG | AMD_CG_SUPPORT_JPEG_MGCG |
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AMD_CG_SUPPORT_IH_CG;
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adev->pg_flags =
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AMD_PG_SUPPORT_VCN |
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AMD_PG_SUPPORT_VCN_DPG |
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AMD_PG_SUPPORT_JPEG;
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adev->external_rev_id = adev->rev_id + 0x46;
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break;
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default:
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/* FIXME: not supported yet */
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return -EINVAL;
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@ -1185,6 +1181,11 @@ static int soc15_common_late_init(void *handle)
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if (amdgpu_sriov_vf(adev))
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xgpu_ai_mailbox_get_irq(adev);
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/* Enable selfring doorbell aperture late because doorbell BAR
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* aperture will change if resize BAR successfully in gmc sw_init.
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*/
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adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true);
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return 0;
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}
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@ -1230,8 +1231,6 @@ static int soc15_common_hw_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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/* enable pcie gen2/3 link */
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soc15_pcie_gen3_enable(adev);
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/* enable aspm */
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soc15_program_aspm(adev);
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/* setup nbio registers */
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@ -1244,7 +1243,8 @@ static int soc15_common_hw_init(void *handle)
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adev->nbio.funcs->remap_hdp_registers(adev);
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/* enable the doorbell aperture */
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soc15_enable_doorbell_aperture(adev, true);
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adev->nbio.funcs->enable_doorbell_aperture(adev, true);
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/* HW doorbell routing policy: doorbell writing not
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* in SDMA/IH/MM/ACV range will be routed to CP. So
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* we need to init SDMA doorbell range prior
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@ -1260,8 +1260,14 @@ static int soc15_common_hw_fini(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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/* disable the doorbell aperture */
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soc15_enable_doorbell_aperture(adev, false);
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/* Disable the doorbell aperture and selfring doorbell aperture
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* separately in hw_fini because soc15_enable_doorbell_aperture
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* has been removed and there is no need to delay disabling
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* selfring doorbell.
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*/
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adev->nbio.funcs->enable_doorbell_aperture(adev, false);
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adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false);
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if (amdgpu_sriov_vf(adev))
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xgpu_ai_mailbox_put_irq(adev);
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