sync with OpenBSD -current
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1651 changed files with 283292 additions and 68089 deletions
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@ -575,60 +575,17 @@ static void sdma_v4_0_setup_ulv(struct amdgpu_device *adev)
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// vega10 real chip need to use PSP to load firmware
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static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
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{
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const char *chip_name;
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char fw_name[30];
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int ret, i;
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DRM_DEBUG("\n");
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switch (adev->ip_versions[SDMA0_HWIP][0]) {
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case IP_VERSION(4, 0, 0):
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chip_name = "vega10";
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break;
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case IP_VERSION(4, 0, 1):
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chip_name = "vega12";
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break;
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case IP_VERSION(4, 2, 0):
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chip_name = "vega20";
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break;
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case IP_VERSION(4, 1, 0):
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case IP_VERSION(4, 1, 1):
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if (adev->apu_flags & AMD_APU_IS_RAVEN2)
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chip_name = "raven2";
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else if (adev->apu_flags & AMD_APU_IS_PICASSO)
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chip_name = "picasso";
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else
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chip_name = "raven";
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break;
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case IP_VERSION(4, 2, 2):
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chip_name = "arcturus";
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break;
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case IP_VERSION(4, 1, 2):
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if (adev->apu_flags & AMD_APU_IS_RENOIR)
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chip_name = "renoir";
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else
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chip_name = "green_sardine";
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break;
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case IP_VERSION(4, 4, 0):
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chip_name = "aldebaran";
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break;
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default:
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BUG();
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}
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for (i = 0; i < adev->sdma.num_instances; i++) {
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if (i == 0)
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snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
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else
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snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i);
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if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) ||
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adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0)) {
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/* Acturus & Aldebaran will leverage the same FW memory
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for every SDMA instance */
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ret = amdgpu_sdma_init_microcode(adev, fw_name, 0, true);
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ret = amdgpu_sdma_init_microcode(adev, 0, true);
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break;
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} else {
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ret = amdgpu_sdma_init_microcode(adev, fw_name, i, false);
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ret = amdgpu_sdma_init_microcode(adev, i, false);
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if (ret)
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return ret;
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}
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@ -1157,8 +1114,6 @@ static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i)
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#endif
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/* enable DMA IBs */
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WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);
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ring->sched.ready = true;
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}
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/**
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@ -1245,8 +1200,6 @@ static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i)
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#endif
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/* enable DMA IBs */
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WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl);
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ring->sched.ready = true;
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}
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static void
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@ -1866,6 +1819,15 @@ static int sdma_v4_0_sw_init(void *handle)
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/* doorbell size is 2 dwords, get DWORD offset */
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ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
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/*
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* On Arcturus, SDMA instance 5~7 has a different vmhub
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* type(AMDGPU_MMHUB1).
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*/
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if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) && i >= 5)
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ring->vm_hub = AMDGPU_MMHUB1(0);
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else
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ring->vm_hub = AMDGPU_MMHUB0(0);
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snprintf(ring->name, sizeof(ring->name), "sdma%d", i);
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r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
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AMDGPU_SDMA_IRQ_INSTANCE0 + i,
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@ -1881,8 +1843,23 @@ static int sdma_v4_0_sw_init(void *handle)
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/* paging queue use same doorbell index/routing as gfx queue
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* with 0x400 (4096 dwords) offset on second doorbell page
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*/
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ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
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ring->doorbell_index += 0x400;
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if (adev->ip_versions[SDMA0_HWIP][0] >= IP_VERSION(4, 0, 0) &&
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adev->ip_versions[SDMA0_HWIP][0] < IP_VERSION(4, 2, 0)) {
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ring->doorbell_index =
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adev->doorbell_index.sdma_engine[i] << 1;
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ring->doorbell_index += 0x400;
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} else {
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/* From vega20, the sdma_doorbell_range in 1st
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* doorbell page is reserved for page queue.
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*/
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ring->doorbell_index =
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(adev->doorbell_index.sdma_engine[i] + 1) << 1;
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}
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if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) && i >= 5)
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ring->vm_hub = AMDGPU_MMHUB1(0);
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else
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ring->vm_hub = AMDGPU_MMHUB0(0);
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snprintf(ring->name, sizeof(ring->name), "page%d", i);
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r = amdgpu_ring_init(adev, ring, 1024,
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@ -1894,6 +1871,11 @@ static int sdma_v4_0_sw_init(void *handle)
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}
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}
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if (amdgpu_sdma_ras_sw_init(adev)) {
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dev_err(adev->dev, "Failed to initialize sdma ras block!\n");
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return -EINVAL;
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}
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return r;
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}
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@ -2334,44 +2316,6 @@ static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
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.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
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.support_64bit_ptrs = true,
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.secure_submission_supported = true,
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.vmhub = AMDGPU_MMHUB_0,
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.get_rptr = sdma_v4_0_ring_get_rptr,
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.get_wptr = sdma_v4_0_ring_get_wptr,
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.set_wptr = sdma_v4_0_ring_set_wptr,
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.emit_frame_size =
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6 + /* sdma_v4_0_ring_emit_hdp_flush */
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3 + /* hdp invalidate */
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6 + /* sdma_v4_0_ring_emit_pipeline_sync */
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/* sdma_v4_0_ring_emit_vm_flush */
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SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
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SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
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10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
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.emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
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.emit_ib = sdma_v4_0_ring_emit_ib,
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.emit_fence = sdma_v4_0_ring_emit_fence,
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.emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
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.emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
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.emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
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.test_ring = sdma_v4_0_ring_test_ring,
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.test_ib = sdma_v4_0_ring_test_ib,
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.insert_nop = sdma_v4_0_ring_insert_nop,
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.pad_ib = sdma_v4_0_ring_pad_ib,
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.emit_wreg = sdma_v4_0_ring_emit_wreg,
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.emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
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.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
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};
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/*
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* On Arcturus, SDMA instance 5~7 has a different vmhub type(AMDGPU_MMHUB_1).
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* So create a individual constant ring_funcs for those instances.
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*/
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static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs_2nd_mmhub = {
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.type = AMDGPU_RING_TYPE_SDMA,
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.align_mask = 0xf,
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.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
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.support_64bit_ptrs = true,
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.secure_submission_supported = true,
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.vmhub = AMDGPU_MMHUB_1,
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.get_rptr = sdma_v4_0_ring_get_rptr,
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.get_wptr = sdma_v4_0_ring_get_wptr,
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.set_wptr = sdma_v4_0_ring_set_wptr,
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@ -2404,40 +2348,6 @@ static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = {
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.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
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.support_64bit_ptrs = true,
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.secure_submission_supported = true,
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.vmhub = AMDGPU_MMHUB_0,
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.get_rptr = sdma_v4_0_ring_get_rptr,
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.get_wptr = sdma_v4_0_page_ring_get_wptr,
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.set_wptr = sdma_v4_0_page_ring_set_wptr,
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.emit_frame_size =
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6 + /* sdma_v4_0_ring_emit_hdp_flush */
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3 + /* hdp invalidate */
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6 + /* sdma_v4_0_ring_emit_pipeline_sync */
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/* sdma_v4_0_ring_emit_vm_flush */
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SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
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SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
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10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
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.emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
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.emit_ib = sdma_v4_0_ring_emit_ib,
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.emit_fence = sdma_v4_0_ring_emit_fence,
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.emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
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.emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
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.emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
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.test_ring = sdma_v4_0_ring_test_ring,
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.test_ib = sdma_v4_0_ring_test_ib,
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.insert_nop = sdma_v4_0_ring_insert_nop,
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.pad_ib = sdma_v4_0_ring_pad_ib,
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.emit_wreg = sdma_v4_0_ring_emit_wreg,
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.emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
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.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
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};
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static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs_2nd_mmhub = {
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.type = AMDGPU_RING_TYPE_SDMA,
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.align_mask = 0xf,
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.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
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.support_64bit_ptrs = true,
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.secure_submission_supported = true,
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.vmhub = AMDGPU_MMHUB_1,
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.get_rptr = sdma_v4_0_ring_get_rptr,
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.get_wptr = sdma_v4_0_page_ring_get_wptr,
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.set_wptr = sdma_v4_0_page_ring_set_wptr,
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@ -2469,19 +2379,10 @@ static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
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int i;
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for (i = 0; i < adev->sdma.num_instances; i++) {
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if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) && i >= 5)
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adev->sdma.instance[i].ring.funcs =
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&sdma_v4_0_ring_funcs_2nd_mmhub;
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else
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adev->sdma.instance[i].ring.funcs =
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&sdma_v4_0_ring_funcs;
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adev->sdma.instance[i].ring.funcs = &sdma_v4_0_ring_funcs;
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adev->sdma.instance[i].ring.me = i;
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if (adev->sdma.has_page_queue) {
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if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) && i >= 5)
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adev->sdma.instance[i].page.funcs =
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&sdma_v4_0_page_ring_funcs_2nd_mmhub;
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else
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adev->sdma.instance[i].page.funcs =
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adev->sdma.instance[i].page.funcs =
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&sdma_v4_0_page_ring_funcs;
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adev->sdma.instance[i].page.me = i;
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}
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@ -2733,23 +2634,6 @@ static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev)
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break;
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}
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if (adev->sdma.ras) {
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amdgpu_ras_register_ras_block(adev, &adev->sdma.ras->ras_block);
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strlcpy(adev->sdma.ras->ras_block.ras_comm.name, "sdma",
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sizeof(adev->sdma.ras->ras_block.ras_comm.name));
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adev->sdma.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__SDMA;
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adev->sdma.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
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adev->sdma.ras_if = &adev->sdma.ras->ras_block.ras_comm;
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/* If don't define special ras_late_init function, use default ras_late_init */
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if (!adev->sdma.ras->ras_block.ras_late_init)
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adev->sdma.ras->ras_block.ras_late_init = amdgpu_sdma_ras_late_init;
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/* If not defined special ras_cb function, use default ras_cb */
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if (!adev->sdma.ras->ras_block.ras_cb)
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adev->sdma.ras->ras_block.ras_cb = amdgpu_sdma_process_ras_data_cb;
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}
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}
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const struct amdgpu_ip_block_version sdma_v4_0_ip_block = {
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