sync with OpenBSD -current
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F42C07F07E2E35B7
1651 changed files with 283292 additions and 68089 deletions
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@ -56,7 +56,8 @@ void amdgpu_virt_init_setting(struct amdgpu_device *adev)
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/* enable virtual display */
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if (adev->asic_type != CHIP_ALDEBARAN &&
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adev->asic_type != CHIP_ARCTURUS) {
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adev->asic_type != CHIP_ARCTURUS &&
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((adev->pdev->class >> 8) != PCI_CLASS_ACCELERATOR_PROCESSING)) {
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if (adev->mode_info.num_crtc == 0)
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adev->mode_info.num_crtc = 1;
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adev->enable_virtual_display = true;
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@ -64,13 +65,17 @@ void amdgpu_virt_init_setting(struct amdgpu_device *adev)
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ddev->driver_features &= ~DRIVER_ATOMIC;
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adev->cg_flags = 0;
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adev->pg_flags = 0;
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/* Reduce kcq number to 2 to reduce latency */
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if (amdgpu_num_kcq == -1)
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amdgpu_num_kcq = 2;
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}
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void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev,
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uint32_t reg0, uint32_t reg1,
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uint32_t ref, uint32_t mask)
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{
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struct amdgpu_kiq *kiq = &adev->gfx.kiq;
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struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
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struct amdgpu_ring *ring = &kiq->ring;
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signed long r, cnt = 0;
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unsigned long flags;
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@ -228,7 +233,8 @@ int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev)
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return 0;
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r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM,
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AMDGPU_GEM_DOMAIN_VRAM |
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AMDGPU_GEM_DOMAIN_GTT,
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&adev->virt.mm_table.bo,
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&adev->virt.mm_table.gpu_addr,
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(void *)&adev->virt.mm_table.cpu_addr);
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@ -423,11 +429,17 @@ static void amdgpu_virt_add_bad_page(struct amdgpu_device *adev,
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struct eeprom_table_record bp;
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uint64_t retired_page;
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uint32_t bp_idx, bp_cnt;
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void *vram_usage_va = NULL;
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if (adev->mman.fw_vram_usage_va)
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vram_usage_va = adev->mman.fw_vram_usage_va;
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else
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vram_usage_va = adev->mman.drv_vram_usage_va;
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if (bp_block_size) {
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bp_cnt = bp_block_size / sizeof(uint64_t);
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for (bp_idx = 0; bp_idx < bp_cnt; bp_idx++) {
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retired_page = *(uint64_t *)(adev->mman.fw_vram_usage_va +
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retired_page = *(uint64_t *)(vram_usage_va +
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bp_block_offset + bp_idx * sizeof(uint64_t));
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bp.retired_page = retired_page;
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@ -508,7 +520,7 @@ static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device *adev)
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tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].encode_max_frame_pixels;
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adev->virt.encode_max_frame_pixels = max(tmp, adev->virt.encode_max_frame_pixels);
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}
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if((adev->virt.decode_max_dimension_pixels > 0) || (adev->virt.encode_max_dimension_pixels > 0))
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if ((adev->virt.decode_max_dimension_pixels > 0) || (adev->virt.encode_max_dimension_pixels > 0))
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adev->virt.is_mm_bw_enabled = true;
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adev->unique_id =
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@ -546,7 +558,6 @@ static void amdgpu_virt_populate_vf2pf_ucode_info(struct amdgpu_device *adev)
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POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLS, adev->gfx.rlc_srls_fw_version);
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POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC, adev->gfx.mec_fw_version);
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POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC2, adev->gfx.mec2_fw_version);
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POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_IMU, adev->gfx.imu_fw_version);
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POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SOS, adev->psp.sos.fw_version);
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POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ASD,
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adev->psp.asd_context.bin_desc.fw_version);
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@ -639,7 +650,9 @@ void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev)
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adev->virt.fw_reserve.p_vf2pf = NULL;
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adev->virt.vf2pf_update_interval_ms = 0;
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if (adev->mman.fw_vram_usage_va != NULL) {
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if (adev->mman.fw_vram_usage_va && adev->mman.drv_vram_usage_va) {
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DRM_WARN("Currently fw_vram and drv_vram should not have values at the same time!");
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} else if (adev->mman.fw_vram_usage_va || adev->mman.drv_vram_usage_va) {
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/* go through this logic in ip_init and reset to init workqueue*/
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amdgpu_virt_exchange_data(adev);
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@ -662,32 +675,40 @@ void amdgpu_virt_exchange_data(struct amdgpu_device *adev)
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uint32_t bp_block_size = 0;
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struct amd_sriov_msg_pf2vf_info *pf2vf_v2 = NULL;
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if (adev->mman.fw_vram_usage_va != NULL) {
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adev->virt.fw_reserve.p_pf2vf =
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(struct amd_sriov_msg_pf2vf_info_header *)
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(adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10));
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adev->virt.fw_reserve.p_vf2pf =
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(struct amd_sriov_msg_vf2pf_info_header *)
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(adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10));
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if (adev->mman.fw_vram_usage_va || adev->mman.drv_vram_usage_va) {
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if (adev->mman.fw_vram_usage_va) {
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adev->virt.fw_reserve.p_pf2vf =
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(struct amd_sriov_msg_pf2vf_info_header *)
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(adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10));
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adev->virt.fw_reserve.p_vf2pf =
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(struct amd_sriov_msg_vf2pf_info_header *)
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(adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10));
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} else if (adev->mman.drv_vram_usage_va) {
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adev->virt.fw_reserve.p_pf2vf =
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(struct amd_sriov_msg_pf2vf_info_header *)
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(adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10));
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adev->virt.fw_reserve.p_vf2pf =
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(struct amd_sriov_msg_vf2pf_info_header *)
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(adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10));
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}
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amdgpu_virt_read_pf2vf_data(adev);
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amdgpu_virt_write_vf2pf_data(adev);
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/* bad page handling for version 2 */
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if (adev->virt.fw_reserve.p_pf2vf->version == 2) {
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pf2vf_v2 = (struct amd_sriov_msg_pf2vf_info *)adev->virt.fw_reserve.p_pf2vf;
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pf2vf_v2 = (struct amd_sriov_msg_pf2vf_info *)adev->virt.fw_reserve.p_pf2vf;
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bp_block_offset = ((uint64_t)pf2vf_v2->bp_block_offset_low & 0xFFFFFFFF) |
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((((uint64_t)pf2vf_v2->bp_block_offset_high) << 32) & 0xFFFFFFFF00000000);
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bp_block_size = pf2vf_v2->bp_block_size;
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bp_block_offset = ((uint64_t)pf2vf_v2->bp_block_offset_low & 0xFFFFFFFF) |
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((((uint64_t)pf2vf_v2->bp_block_offset_high) << 32) & 0xFFFFFFFF00000000);
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bp_block_size = pf2vf_v2->bp_block_size;
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if (bp_block_size && !adev->virt.ras_init_done)
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amdgpu_virt_init_ras_err_handler_data(adev);
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if (bp_block_size && !adev->virt.ras_init_done)
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amdgpu_virt_init_ras_err_handler_data(adev);
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if (adev->virt.ras_init_done)
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amdgpu_virt_add_bad_page(adev, bp_block_offset, bp_block_size);
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}
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if (adev->virt.ras_init_done)
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amdgpu_virt_add_bad_page(adev, bp_block_offset, bp_block_size);
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}
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}
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}
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@ -815,6 +836,16 @@ enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *ad
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return mode;
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}
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void amdgpu_virt_post_reset(struct amdgpu_device *adev)
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{
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if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 3)) {
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/* force set to GFXOFF state after reset,
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* to avoid some invalid operation before GC enable
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*/
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adev->gfx.is_poweron = false;
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}
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}
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bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, uint32_t ucode_id)
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{
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switch (adev->ip_versions[MP0_HWIP][0]) {
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@ -825,6 +856,17 @@ bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, uint32_t ucode_i
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return false;
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else
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return true;
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case IP_VERSION(11, 0, 9):
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case IP_VERSION(11, 0, 7):
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/* black list for CHIP_NAVI12 and CHIP_SIENNA_CICHLID */
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if (ucode_id == AMDGPU_UCODE_ID_RLC_G
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|| ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
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|| ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
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|| ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
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|| ucode_id == AMDGPU_UCODE_ID_SMC)
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return true;
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else
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return false;
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case IP_VERSION(13, 0, 10):
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/* white list */
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if (ucode_id == AMDGPU_UCODE_ID_CAP
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@ -934,7 +976,7 @@ static bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev,
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return ret;
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}
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static u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag)
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static u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id)
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{
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struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
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uint32_t timeout = 50000;
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@ -952,7 +994,12 @@ static u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v
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return 0;
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}
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reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl;
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if (adev->gfx.xcc_mask && (((1 << xcc_id) & adev->gfx.xcc_mask) == 0)) {
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dev_err(adev->dev, "invalid xcc\n");
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return 0;
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}
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reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[xcc_id];
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scratch_reg0 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg0;
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scratch_reg1 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg1;
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scratch_reg2 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg2;
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@ -963,11 +1010,13 @@ static u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v
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if (offset == reg_access_ctrl->grbm_cntl) {
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/* if the target reg offset is grbm_cntl, write to scratch_reg2 */
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writel(v, scratch_reg2);
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writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));
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if (flag == AMDGPU_RLCG_GC_WRITE_LEGACY)
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writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));
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} else if (offset == reg_access_ctrl->grbm_idx) {
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/* if the target reg offset is grbm_idx, write to scratch_reg3 */
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writel(v, scratch_reg3);
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writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));
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if (flag == AMDGPU_RLCG_GC_WRITE_LEGACY)
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writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));
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} else {
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/*
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* SCRATCH_REG0 = read/write value
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@ -1015,13 +1064,13 @@ static u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v
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void amdgpu_sriov_wreg(struct amdgpu_device *adev,
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u32 offset, u32 value,
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u32 acc_flags, u32 hwip)
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u32 acc_flags, u32 hwip, u32 xcc_id)
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{
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u32 rlcg_flag;
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if (!amdgpu_sriov_runtime(adev) &&
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amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, true, &rlcg_flag)) {
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amdgpu_virt_rlcg_reg_rw(adev, offset, value, rlcg_flag);
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amdgpu_virt_rlcg_reg_rw(adev, offset, value, rlcg_flag, xcc_id);
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return;
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}
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@ -1032,13 +1081,13 @@ void amdgpu_sriov_wreg(struct amdgpu_device *adev,
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}
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u32 amdgpu_sriov_rreg(struct amdgpu_device *adev,
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u32 offset, u32 acc_flags, u32 hwip)
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u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id)
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{
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u32 rlcg_flag;
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if (!amdgpu_sriov_runtime(adev) &&
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amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, false, &rlcg_flag))
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return amdgpu_virt_rlcg_reg_rw(adev, offset, 0, rlcg_flag);
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return amdgpu_virt_rlcg_reg_rw(adev, offset, 0, rlcg_flag, xcc_id);
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if (acc_flags & AMDGPU_REGS_NO_KIQ)
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return RREG32_NO_KIQ(offset);
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