sync with OpenBSD -current
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GPG key ID:
F42C07F07E2E35B7
1651 changed files with 283292 additions and 68089 deletions
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@ -33,6 +33,7 @@
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#include "amdgpu_imu.h"
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#include "soc15.h"
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#include "amdgpu_ras.h"
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#include "amdgpu_ring_mux.h"
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/* GFX current status */
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#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
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@ -41,6 +42,9 @@
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#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
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#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
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#define AMDGPU_MAX_GC_INSTANCES 8
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#define KGD_MAX_QUEUES 128
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#define AMDGPU_MAX_GFX_QUEUES KGD_MAX_QUEUES
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#define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
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@ -52,6 +56,50 @@ enum amdgpu_gfx_pipe_priority {
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#define AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM 0
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#define AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM 15
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enum amdgpu_gfx_partition {
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AMDGPU_SPX_PARTITION_MODE = 0,
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AMDGPU_DPX_PARTITION_MODE = 1,
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AMDGPU_TPX_PARTITION_MODE = 2,
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AMDGPU_QPX_PARTITION_MODE = 3,
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AMDGPU_CPX_PARTITION_MODE = 4,
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AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE = -1,
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/* Automatically choose the right mode */
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AMDGPU_AUTO_COMPUTE_PARTITION_MODE = -2,
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};
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#define NUM_XCC(x) hweight16(x)
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enum amdgpu_pkg_type {
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AMDGPU_PKG_TYPE_APU = 2,
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AMDGPU_PKG_TYPE_UNKNOWN,
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};
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enum amdgpu_gfx_ras_mem_id_type {
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AMDGPU_GFX_CP_MEM = 0,
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AMDGPU_GFX_GCEA_MEM,
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AMDGPU_GFX_GC_CANE_MEM,
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AMDGPU_GFX_GCUTCL2_MEM,
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AMDGPU_GFX_GDS_MEM,
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AMDGPU_GFX_LDS_MEM,
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AMDGPU_GFX_RLC_MEM,
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AMDGPU_GFX_SP_MEM,
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AMDGPU_GFX_SPI_MEM,
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AMDGPU_GFX_SQC_MEM,
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AMDGPU_GFX_SQ_MEM,
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AMDGPU_GFX_TA_MEM,
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AMDGPU_GFX_TCC_MEM,
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AMDGPU_GFX_TCA_MEM,
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AMDGPU_GFX_TCI_MEM,
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AMDGPU_GFX_TCP_MEM,
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AMDGPU_GFX_TD_MEM,
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AMDGPU_GFX_TCX_MEM,
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AMDGPU_GFX_ATC_L2_MEM,
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AMDGPU_GFX_UTCL2_MEM,
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AMDGPU_GFX_VML2_MEM,
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AMDGPU_GFX_VML2_WALKER_MEM,
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AMDGPU_GFX_MEM_TYPE_NUM
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};
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struct amdgpu_mec {
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struct amdgpu_bo *hpd_eop_obj;
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u64 hpd_eop_gpu_addr;
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@ -63,8 +111,10 @@ struct amdgpu_mec {
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u32 num_mec;
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u32 num_pipe_per_mec;
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u32 num_queue_per_pipe;
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void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];
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void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS * AMDGPU_MAX_GC_INSTANCES];
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};
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struct amdgpu_mec_bitmap {
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/* These are the resources for which amdgpu takes ownership */
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DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
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};
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@ -108,6 +158,7 @@ struct amdgpu_kiq {
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struct amdgpu_ring ring;
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struct amdgpu_irq_src irq;
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const struct kiq_pm4_funcs *pmf;
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void *mqd_backup;
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};
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/*
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@ -177,6 +228,8 @@ struct amdgpu_gfx_config {
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uint32_t num_sc_per_sh;
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uint32_t num_packer_per_sc;
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uint32_t pa_sc_tile_steering_override;
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/* Whether texture coordinate truncation is conformant. */
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bool ta_cntl2_truncate_coord_mode;
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uint64_t tcc_disabled_mask;
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uint32_t gc_num_tcp_per_sa;
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uint32_t gc_num_sdp_interface;
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@ -189,6 +242,9 @@ struct amdgpu_gfx_config {
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uint32_t gc_gl1c_per_sa;
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uint32_t gc_gl1c_size_per_instance;
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uint32_t gc_gl2c_per_gpu;
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uint32_t gc_tcp_size_per_cu;
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uint32_t gc_num_cu_per_sqc;
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uint32_t gc_tcc_size;
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};
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struct amdgpu_cu_info {
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@ -202,32 +258,51 @@ struct amdgpu_cu_info {
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uint32_t number;
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uint32_t ao_cu_mask;
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uint32_t ao_cu_bitmap[4][4];
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uint32_t bitmap[4][4];
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uint32_t bitmap[AMDGPU_MAX_GC_INSTANCES][4][4];
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};
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struct amdgpu_gfx_ras {
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struct amdgpu_ras_block_object ras_block;
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void (*enable_watchdog_timer)(struct amdgpu_device *adev);
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bool (*query_utcl2_poison_status)(struct amdgpu_device *adev);
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int (*rlc_gc_fed_irq)(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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struct amdgpu_iv_entry *entry);
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int (*poison_consumption_handler)(struct amdgpu_device *adev,
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struct amdgpu_iv_entry *entry);
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};
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struct amdgpu_gfx_shadow_info {
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u32 shadow_size;
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u32 shadow_alignment;
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u32 csa_size;
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u32 csa_alignment;
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};
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struct amdgpu_gfx_funcs {
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/* get the gpu clock counter */
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uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
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void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num,
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u32 sh_num, u32 instance);
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void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd,
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u32 sh_num, u32 instance, int xcc_id);
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void (*read_wave_data)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
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uint32_t wave, uint32_t *dst, int *no_fields);
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void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd,
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void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
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uint32_t wave, uint32_t thread, uint32_t start,
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uint32_t size, uint32_t *dst);
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void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd,
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void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
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uint32_t wave, uint32_t start, uint32_t size,
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uint32_t *dst);
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void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe,
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u32 queue, u32 vmid);
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u32 queue, u32 vmid, u32 xcc_id);
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void (*init_spm_golden)(struct amdgpu_device *adev);
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void (*update_perfmon_mgcg)(struct amdgpu_device *adev, bool enable);
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int (*get_gfx_shadow_info)(struct amdgpu_device *adev,
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struct amdgpu_gfx_shadow_info *shadow_info);
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enum amdgpu_gfx_partition
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(*query_partition_mode)(struct amdgpu_device *adev);
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int (*switch_partition_mode)(struct amdgpu_device *adev,
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int num_xccs_per_xcp);
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int (*ih_node_to_logical_xcc)(struct amdgpu_device *adev, int ih_node);
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};
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struct sq_work {
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@ -277,7 +352,8 @@ struct amdgpu_gfx {
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struct amdgpu_ce ce;
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struct amdgpu_me me;
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struct amdgpu_mec mec;
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struct amdgpu_kiq kiq;
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struct amdgpu_mec_bitmap mec_bitmap[AMDGPU_MAX_GC_INSTANCES];
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struct amdgpu_kiq kiq[AMDGPU_MAX_GC_INSTANCES];
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struct amdgpu_imu imu;
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bool rs64_enable; /* firmware format */
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const struct firmware *me_fw; /* ME firmware */
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@ -315,13 +391,14 @@ struct amdgpu_gfx {
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bool cp_fw_write_wait;
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struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
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unsigned num_gfx_rings;
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struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
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struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS * AMDGPU_MAX_GC_INSTANCES];
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unsigned num_compute_rings;
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struct amdgpu_irq_src eop_irq;
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struct amdgpu_irq_src priv_reg_irq;
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struct amdgpu_irq_src priv_inst_irq;
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struct amdgpu_irq_src cp_ecc_error_irq;
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struct amdgpu_irq_src sq_irq;
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struct amdgpu_irq_src rlc_gc_fed_irq;
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struct sq_work sq_work;
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/* gfx status */
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struct amdgpu_gfx_ras *ras;
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bool is_poweron;
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struct amdgpu_ring sw_gfx_ring[AMDGPU_MAX_SW_GFX_RINGS];
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struct amdgpu_ring_mux muxer;
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bool cp_gfx_shadow; /* for gfx11 */
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uint16_t xcc_mask;
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uint32_t num_xcc_per_xcp;
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struct rwlock partition_mutex;
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bool mcbp; /* mid command buffer preemption */
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};
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struct amdgpu_gfx_ras_reg_entry {
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struct amdgpu_ras_err_status_reg_entry reg_entry;
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enum amdgpu_gfx_ras_mem_id_type mem_id_type;
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uint32_t se_num;
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};
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struct amdgpu_gfx_ras_mem_id_entry {
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const struct amdgpu_ras_memory_id_entry *mem_id_ent;
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uint32_t size;
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};
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#define AMDGPU_GFX_MEMID_ENT(x) {(x), ARRAY_SIZE(x)},
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#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
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#define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
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#define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid))
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#define amdgpu_gfx_select_se_sh(adev, se, sh, instance, xcc_id) ((adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance), (xcc_id)))
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#define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid, xcc_id) ((adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid), (xcc_id)))
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#define amdgpu_gfx_init_spm_golden(adev) (adev)->gfx.funcs->init_spm_golden((adev))
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#define amdgpu_gfx_get_gfx_shadow_info(adev, si) ((adev)->gfx.funcs->get_gfx_shadow_info((adev), (si)))
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/**
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* amdgpu_gfx_create_bitmask - create a bitmask
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@ -377,19 +478,21 @@ void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se,
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int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
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struct amdgpu_ring *ring,
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struct amdgpu_irq_src *irq);
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struct amdgpu_irq_src *irq, int xcc_id);
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void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring);
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void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev);
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void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev, int xcc_id);
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int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
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unsigned hpd_size);
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unsigned hpd_size, int xcc_id);
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int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
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unsigned mqd_size);
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void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev);
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int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev);
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int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev);
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unsigned mqd_size, int xcc_id);
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void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev, int xcc_id);
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int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev, int xcc_id);
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int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev, int xcc_id);
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int amdgpu_gfx_disable_kgq(struct amdgpu_device *adev, int xcc_id);
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int amdgpu_gfx_enable_kgq(struct amdgpu_device *adev, int xcc_id);
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void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev);
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void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev);
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@ -398,8 +501,8 @@ int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec,
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int pipe, int queue);
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void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
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int *mec, int *pipe, int *queue);
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bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec,
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int pipe, int queue);
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bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int xcc_id,
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int mec, int pipe, int queue);
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bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
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struct amdgpu_ring *ring);
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bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev,
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@ -428,4 +531,36 @@ void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
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int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev);
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void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev, uint32_t ucode_id);
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int amdgpu_gfx_ras_sw_init(struct amdgpu_device *adev);
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int amdgpu_gfx_poison_consumption_handler(struct amdgpu_device *adev,
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struct amdgpu_iv_entry *entry);
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bool amdgpu_gfx_is_master_xcc(struct amdgpu_device *adev, int xcc_id);
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int amdgpu_gfx_sysfs_init(struct amdgpu_device *adev);
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void amdgpu_gfx_sysfs_fini(struct amdgpu_device *adev);
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void amdgpu_gfx_ras_error_func(struct amdgpu_device *adev,
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void *ras_error_status,
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void (*func)(struct amdgpu_device *adev, void *ras_error_status,
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int xcc_id));
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static inline const char *amdgpu_gfx_compute_mode_desc(int mode)
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{
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switch (mode) {
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case AMDGPU_SPX_PARTITION_MODE:
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return "SPX";
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case AMDGPU_DPX_PARTITION_MODE:
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return "DPX";
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case AMDGPU_TPX_PARTITION_MODE:
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return "TPX";
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case AMDGPU_QPX_PARTITION_MODE:
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return "QPX";
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case AMDGPU_CPX_PARTITION_MODE:
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return "CPX";
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default:
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return "UNKNOWN";
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}
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return "UNKNOWN";
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}
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#endif
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