sync with OpenBSD -current
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1cefe29c7e
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F42C07F07E2E35B7
1651 changed files with 283292 additions and 68089 deletions
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@ -58,7 +58,6 @@ int amdgpu_amdkfd_init(void)
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amdgpu_amdkfd_total_mem_size = ptoa(physmem);
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#endif
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ret = kgd2kfd_init();
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amdgpu_amdkfd_gpuvm_init_mem_limits();
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kfd_initialized = !ret;
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return ret;
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@ -101,7 +100,7 @@ static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
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size_t *start_offset)
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{
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/*
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* The first num_doorbells are used by amdgpu.
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* The first num_kernel_doorbells are used by amdgpu.
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* amdkfd takes whatever's left in the aperture.
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*/
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if (adev->enable_mes) {
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@ -114,11 +113,11 @@ static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
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*aperture_base = adev->doorbell.base;
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*aperture_size = 0;
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*start_offset = 0;
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} else if (adev->doorbell.size > adev->doorbell.num_doorbells *
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} else if (adev->doorbell.size > adev->doorbell.num_kernel_doorbells *
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sizeof(u32)) {
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*aperture_base = adev->doorbell.base;
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*aperture_size = adev->doorbell.size;
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*start_offset = adev->doorbell.num_doorbells * sizeof(u32);
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*start_offset = adev->doorbell.num_kernel_doorbells * sizeof(u32);
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} else {
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*aperture_base = 0;
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*aperture_size = 0;
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@ -148,6 +147,8 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
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int i;
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int last_valid_bit;
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amdgpu_amdkfd_gpuvm_init_mem_limits();
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if (adev->kfd.dev) {
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struct kgd2kfd_shared_resources gpu_resources = {
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.compute_vmid_bitmap =
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@ -167,7 +168,7 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
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* clear
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*/
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bitmap_complement(gpu_resources.cp_queue_bitmap,
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adev->gfx.mec.queue_bitmap,
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adev->gfx.mec_bitmap[0].queue_bitmap,
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KGD_MAX_QUEUES);
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/* According to linux/bitmap.h we shouldn't use bitmap_clear if
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@ -200,7 +201,7 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
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}
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adev->kfd.init_complete = kgd2kfd_device_init(adev->kfd.dev,
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adev_to_drm(adev), &gpu_resources);
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&gpu_resources);
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amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size;
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@ -230,16 +231,6 @@ void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm)
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kgd2kfd_suspend(adev->kfd.dev, run_pm);
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}
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int amdgpu_amdkfd_resume_iommu(struct amdgpu_device *adev)
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{
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int r = 0;
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if (adev->kfd.dev)
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r = kgd2kfd_resume_iommu(adev->kfd.dev);
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return r;
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}
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int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm)
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{
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int r = 0;
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@ -432,14 +423,23 @@ uint32_t amdgpu_amdkfd_get_fw_version(struct amdgpu_device *adev,
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}
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void amdgpu_amdkfd_get_local_mem_info(struct amdgpu_device *adev,
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struct kfd_local_mem_info *mem_info)
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struct kfd_local_mem_info *mem_info,
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struct amdgpu_xcp *xcp)
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{
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memset(mem_info, 0, sizeof(*mem_info));
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mem_info->local_mem_size_public = adev->gmc.visible_vram_size;
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mem_info->local_mem_size_private = adev->gmc.real_vram_size -
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if (xcp) {
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if (adev->gmc.real_vram_size == adev->gmc.visible_vram_size)
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mem_info->local_mem_size_public =
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KFD_XCP_MEMORY_SIZE(adev, xcp->id);
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else
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mem_info->local_mem_size_private =
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KFD_XCP_MEMORY_SIZE(adev, xcp->id);
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} else {
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mem_info->local_mem_size_public = adev->gmc.visible_vram_size;
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mem_info->local_mem_size_private = adev->gmc.real_vram_size -
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adev->gmc.visible_vram_size;
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}
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mem_info->vram_width = adev->gmc.vram_width;
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pr_debug("Address base: %pap public 0x%llx private 0x%llx\n",
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@ -447,9 +447,7 @@ void amdgpu_amdkfd_get_local_mem_info(struct amdgpu_device *adev,
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mem_info->local_mem_size_public,
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mem_info->local_mem_size_private);
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if (amdgpu_sriov_vf(adev))
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mem_info->mem_clk_max = adev->clock.default_mclk / 100;
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else if (adev->pm.dpm_enabled) {
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if (adev->pm.dpm_enabled) {
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if (amdgpu_emu_mode == 1)
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mem_info->mem_clk_max = 0;
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else
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@ -468,9 +466,7 @@ uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct amdgpu_device *adev)
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uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct amdgpu_device *adev)
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{
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/* the sclk is in quantas of 10kHz */
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if (amdgpu_sriov_vf(adev))
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return adev->clock.default_sclk / 100;
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else if (adev->pm.dpm_enabled)
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if (adev->pm.dpm_enabled)
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return amdgpu_dpm_get_sclk(adev, false) / 100;
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else
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return 100;
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@ -487,7 +483,7 @@ void amdgpu_amdkfd_get_cu_info(struct amdgpu_device *adev, struct kfd_cu_info *c
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cu_info->cu_active_number = acu_info.number;
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cu_info->cu_ao_mask = acu_info.ao_cu_mask;
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memcpy(&cu_info->cu_bitmap[0], &acu_info.bitmap[0],
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sizeof(acu_info.bitmap));
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sizeof(cu_info->cu_bitmap));
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cu_info->num_shader_engines = adev->gfx.config.max_shader_engines;
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cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
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cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
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@ -502,7 +498,7 @@ int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd,
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struct amdgpu_device **dmabuf_adev,
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uint64_t *bo_size, void *metadata_buffer,
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size_t buffer_size, uint32_t *metadata_size,
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uint32_t *flags)
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uint32_t *flags, int8_t *xcp_id)
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{
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struct dma_buf *dma_buf;
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struct drm_gem_object *obj;
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@ -546,6 +542,8 @@ int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd,
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if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
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*flags |= KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC;
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}
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if (xcp_id)
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*xcp_id = bo->xcp_id;
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out_put:
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dma_buf_put(dma_buf);
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@ -678,7 +676,7 @@ int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev,
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goto err;
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}
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ret = amdgpu_job_alloc(adev, 1, &job, NULL);
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ret = amdgpu_job_alloc(adev, NULL, NULL, NULL, 1, &job);
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if (ret)
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goto err;
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@ -737,17 +735,19 @@ int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct amdgpu_device *adev,
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if (adev->family == AMDGPU_FAMILY_AI) {
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int i;
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for (i = 0; i < adev->num_vmhubs; i++)
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for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS)
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amdgpu_gmc_flush_gpu_tlb(adev, vmid, i, 0);
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} else {
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amdgpu_gmc_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB_0, 0);
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amdgpu_gmc_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB(0), 0);
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}
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return 0;
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}
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int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
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uint16_t pasid, enum TLB_FLUSH_TYPE flush_type)
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uint16_t pasid,
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enum TLB_FLUSH_TYPE flush_type,
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uint32_t inst)
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{
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bool all_hub = false;
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@ -755,7 +755,7 @@ int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
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adev->family == AMDGPU_FAMILY_RV)
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all_hub = true;
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return amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, flush_type, all_hub);
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return amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, flush_type, all_hub, inst);
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}
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bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev)
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@ -763,11 +763,30 @@ bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev)
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return adev->have_atomics_support;
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}
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void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device *adev)
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{
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amdgpu_device_flush_hdp(adev, NULL);
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}
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void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev, bool reset)
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{
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struct ras_err_data err_data = {0, 0, 0, NULL};
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amdgpu_umc_poison_handler(adev, reset);
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}
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amdgpu_umc_poison_handler(adev, &err_data, reset);
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int amdgpu_amdkfd_send_close_event_drain_irq(struct amdgpu_device *adev,
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uint32_t *payload)
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{
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int ret;
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/* Device or IH ring is not ready so bail. */
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ret = amdgpu_ih_wait_on_checkpoint_process_ts(adev, &adev->irq.ih);
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if (ret)
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return ret;
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/* Send payload to fence KFD interrupts */
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amdgpu_amdkfd_interrupt(adev, payload);
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return 0;
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}
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bool amdgpu_amdkfd_ras_query_utcl2_poison_status(struct amdgpu_device *adev)
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@ -777,3 +796,78 @@ bool amdgpu_amdkfd_ras_query_utcl2_poison_status(struct amdgpu_device *adev)
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else
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return false;
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}
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int amdgpu_amdkfd_check_and_lock_kfd(struct amdgpu_device *adev)
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{
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return kgd2kfd_check_and_lock_kfd();
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}
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void amdgpu_amdkfd_unlock_kfd(struct amdgpu_device *adev)
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{
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kgd2kfd_unlock_kfd();
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}
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u64 amdgpu_amdkfd_xcp_memory_size(struct amdgpu_device *adev, int xcp_id)
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{
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u64 tmp;
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s8 mem_id = KFD_XCP_MEM_ID(adev, xcp_id);
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if (adev->gmc.num_mem_partitions && xcp_id >= 0 && mem_id >= 0) {
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tmp = adev->gmc.mem_partitions[mem_id].size;
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do_div(tmp, adev->xcp_mgr->num_xcp_per_mem_partition);
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return ALIGN_DOWN(tmp, PAGE_SIZE);
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} else {
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return adev->gmc.real_vram_size;
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}
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}
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int amdgpu_amdkfd_unmap_hiq(struct amdgpu_device *adev, u32 doorbell_off,
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u32 inst)
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{
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struct amdgpu_kiq *kiq = &adev->gfx.kiq[inst];
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struct amdgpu_ring *kiq_ring = &kiq->ring;
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struct amdgpu_ring_funcs *ring_funcs;
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struct amdgpu_ring *ring;
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int r = 0;
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if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
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return -EINVAL;
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ring_funcs = kzalloc(sizeof(*ring_funcs), GFP_KERNEL);
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if (!ring_funcs)
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return -ENOMEM;
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ring = kzalloc(sizeof(*ring), GFP_KERNEL);
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if (!ring) {
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r = -ENOMEM;
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goto free_ring_funcs;
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}
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ring_funcs->type = AMDGPU_RING_TYPE_COMPUTE;
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ring->doorbell_index = doorbell_off;
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ring->funcs = ring_funcs;
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spin_lock(&kiq->ring_lock);
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if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
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spin_unlock(&kiq->ring_lock);
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r = -ENOMEM;
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goto free_ring;
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}
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kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES, 0, 0);
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if (kiq_ring->sched.ready && !adev->job_hang)
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r = amdgpu_ring_test_helper(kiq_ring);
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spin_unlock(&kiq->ring_lock);
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free_ring:
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kfree(ring);
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free_ring_funcs:
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kfree(ring_funcs);
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return r;
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}
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