sync with OpenBSD -current
This commit is contained in:
parent
b5356a44af
commit
12fde4069b
187 changed files with 1127 additions and 1365 deletions
|
@ -300,12 +300,15 @@ static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job)
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dma_fence_set_error(finished, -ECANCELED);
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if (finished->error < 0) {
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DRM_INFO("Skip scheduling IBs!\n");
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dev_dbg(adev->dev, "Skip scheduling IBs in ring(%s)",
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ring->name);
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} else {
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r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job,
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&fence);
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if (r)
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DRM_ERROR("Error scheduling IBs (%d)\n", r);
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dev_err(adev->dev,
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"Error scheduling IBs (%d) in ring(%s)", r,
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ring->name);
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}
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job->job_run_counter++;
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@ -1269,14 +1269,18 @@ int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
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* amdgpu_bo_move_notify - notification about a memory move
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* @bo: pointer to a buffer object
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* @evict: if this move is evicting the buffer from the graphics address space
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* @new_mem: new resource for backing the BO
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*
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* Marks the corresponding &amdgpu_bo buffer object as invalid, also performs
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* bookkeeping.
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* TTM driver callback which is called when ttm moves a buffer.
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*/
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void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, bool evict)
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void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
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bool evict,
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struct ttm_resource *new_mem)
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{
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struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
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struct ttm_resource *old_mem = bo->resource;
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struct amdgpu_bo *abo;
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if (!amdgpu_bo_is_amdgpu_bo(bo))
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@ -1289,13 +1293,13 @@ void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, bool evict)
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#ifdef notyet
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if (abo->tbo.base.dma_buf && !abo->tbo.base.import_attach &&
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bo->resource->mem_type != TTM_PL_SYSTEM)
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old_mem && old_mem->mem_type != TTM_PL_SYSTEM)
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dma_buf_move_notify(abo->tbo.base.dma_buf);
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#endif
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/* remember the eviction */
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if (evict)
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atomic64_inc(&adev->num_evictions);
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/* move_notify is called before move happens */
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trace_amdgpu_bo_move(abo, new_mem ? new_mem->mem_type : -1,
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old_mem ? old_mem->mem_type : -1);
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}
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void amdgpu_bo_get_memory(struct amdgpu_bo *bo,
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@ -329,7 +329,9 @@ int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
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int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
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size_t buffer_size, uint32_t *metadata_size,
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uint64_t *flags);
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void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, bool evict);
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void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
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bool evict,
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struct ttm_resource *new_mem);
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void amdgpu_bo_release_notify(struct ttm_buffer_object *bo);
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vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
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void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
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@ -424,7 +424,7 @@ bool amdgpu_res_cpu_visible(struct amdgpu_device *adev,
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return false;
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if (res->mem_type == TTM_PL_SYSTEM || res->mem_type == TTM_PL_TT ||
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res->mem_type == AMDGPU_PL_PREEMPT)
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res->mem_type == AMDGPU_PL_PREEMPT || res->mem_type == AMDGPU_PL_DOORBELL)
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return true;
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if (res->mem_type != TTM_PL_VRAM)
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@ -432,7 +432,7 @@ bool amdgpu_res_cpu_visible(struct amdgpu_device *adev,
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amdgpu_res_first(res, 0, res->size, &cursor);
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while (cursor.remaining) {
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if ((cursor.start + cursor.size) >= adev->gmc.visible_vram_size)
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if ((cursor.start + cursor.size) > adev->gmc.visible_vram_size)
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return false;
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amdgpu_res_next(&cursor, cursor.size);
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}
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@ -486,14 +486,16 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
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if (!old_mem || (old_mem->mem_type == TTM_PL_SYSTEM &&
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bo->ttm == NULL)) {
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amdgpu_bo_move_notify(bo, evict, new_mem);
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ttm_bo_move_null(bo, new_mem);
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goto out;
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return 0;
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}
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if (old_mem->mem_type == TTM_PL_SYSTEM &&
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(new_mem->mem_type == TTM_PL_TT ||
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new_mem->mem_type == AMDGPU_PL_PREEMPT)) {
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amdgpu_bo_move_notify(bo, evict, new_mem);
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ttm_bo_move_null(bo, new_mem);
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goto out;
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return 0;
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}
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if ((old_mem->mem_type == TTM_PL_TT ||
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old_mem->mem_type == AMDGPU_PL_PREEMPT) &&
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@ -503,9 +505,10 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
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return r;
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amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm);
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amdgpu_bo_move_notify(bo, evict, new_mem);
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ttm_resource_free(bo, &bo->resource);
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ttm_bo_assign_mem(bo, new_mem);
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goto out;
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return 0;
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}
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if (old_mem->mem_type == AMDGPU_PL_GDS ||
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@ -517,8 +520,9 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
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new_mem->mem_type == AMDGPU_PL_OA ||
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new_mem->mem_type == AMDGPU_PL_DOORBELL) {
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/* Nothing to save here */
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amdgpu_bo_move_notify(bo, evict, new_mem);
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ttm_bo_move_null(bo, new_mem);
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goto out;
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return 0;
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}
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if (bo->type == ttm_bo_type_device &&
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@ -530,23 +534,24 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
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abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
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}
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if (adev->mman.buffer_funcs_enabled) {
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if (((old_mem->mem_type == TTM_PL_SYSTEM &&
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new_mem->mem_type == TTM_PL_VRAM) ||
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(old_mem->mem_type == TTM_PL_VRAM &&
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new_mem->mem_type == TTM_PL_SYSTEM))) {
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hop->fpfn = 0;
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hop->lpfn = 0;
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hop->mem_type = TTM_PL_TT;
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hop->flags = TTM_PL_FLAG_TEMPORARY;
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return -EMULTIHOP;
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}
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r = amdgpu_move_blit(bo, evict, new_mem, old_mem);
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} else {
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r = -ENODEV;
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if (adev->mman.buffer_funcs_enabled &&
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((old_mem->mem_type == TTM_PL_SYSTEM &&
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new_mem->mem_type == TTM_PL_VRAM) ||
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(old_mem->mem_type == TTM_PL_VRAM &&
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new_mem->mem_type == TTM_PL_SYSTEM))) {
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hop->fpfn = 0;
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hop->lpfn = 0;
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hop->mem_type = TTM_PL_TT;
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hop->flags = TTM_PL_FLAG_TEMPORARY;
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return -EMULTIHOP;
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}
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amdgpu_bo_move_notify(bo, evict, new_mem);
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if (adev->mman.buffer_funcs_enabled)
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r = amdgpu_move_blit(bo, evict, new_mem, old_mem);
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else
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r = -ENODEV;
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if (r) {
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/* Check that all memory is CPU accessible */
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if (!amdgpu_res_copyable(adev, old_mem) ||
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@ -560,11 +565,10 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
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return r;
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}
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trace_amdgpu_bo_move(abo, new_mem->mem_type, old_mem->mem_type);
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out:
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/* update statistics */
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/* update statistics after the move */
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if (evict)
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atomic64_inc(&adev->num_evictions);
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atomic64_add(bo->base.size, &adev->num_bytes_moved);
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amdgpu_bo_move_notify(bo, evict);
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return 0;
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}
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@ -1605,7 +1609,7 @@ static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
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static void
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amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo)
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{
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amdgpu_bo_move_notify(bo, false);
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amdgpu_bo_move_notify(bo, false, NULL);
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}
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static struct ttm_device_funcs amdgpu_bo_driver = {
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@ -61,6 +61,11 @@ void aqua_vanjaram_doorbell_index_init(struct amdgpu_device *adev)
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adev->doorbell_index.max_assignment = AMDGPU_DOORBELL_LAYOUT1_MAX_ASSIGNMENT << 1;
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}
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static bool aqua_vanjaram_xcp_vcn_shared(struct amdgpu_device *adev)
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{
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return (adev->xcp_mgr->num_xcps > adev->vcn.num_vcn_inst);
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}
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static void aqua_vanjaram_set_xcp_id(struct amdgpu_device *adev,
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uint32_t inst_idx, struct amdgpu_ring *ring)
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{
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case AMDGPU_RING_TYPE_VCN_ENC:
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case AMDGPU_RING_TYPE_VCN_JPEG:
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ip_blk = AMDGPU_XCP_VCN;
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if (adev->xcp_mgr->mode == AMDGPU_CPX_PARTITION_MODE)
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if (aqua_vanjaram_xcp_vcn_shared(adev))
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inst_mask = 1 << (inst_idx * 2);
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break;
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default:
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@ -139,10 +144,12 @@ static int aqua_vanjaram_xcp_sched_list_update(
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aqua_vanjaram_xcp_gpu_sched_update(adev, ring, ring->xcp_id);
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/* VCN is shared by two partitions under CPX MODE */
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/* VCN may be shared by two partitions under CPX MODE in certain
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* configs.
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*/
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if ((ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC ||
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ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG) &&
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adev->xcp_mgr->mode == AMDGPU_CPX_PARTITION_MODE)
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ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG) &&
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aqua_vanjaram_xcp_vcn_shared(adev))
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aqua_vanjaram_xcp_gpu_sched_update(adev, ring, ring->xcp_id + 1);
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}
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@ -1613,19 +1613,9 @@ static int sdma_v4_4_2_set_ecc_irq_state(struct amdgpu_device *adev,
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u32 sdma_cntl;
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sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL);
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switch (state) {
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case AMDGPU_IRQ_STATE_DISABLE:
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sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL,
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DRAM_ECC_INT_ENABLE, 0);
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WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl);
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break;
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/* sdma ecc interrupt is enabled by default
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* driver doesn't need to do anything to
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* enable the interrupt */
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case AMDGPU_IRQ_STATE_ENABLE:
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default:
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break;
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}
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sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, DRAM_ECC_INT_ENABLE,
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state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
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WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl);
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return 0;
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}
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@ -1138,7 +1138,7 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep,
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goto err_unlock;
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}
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offset = dev->adev->rmmio_remap.bus_addr;
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if (!offset) {
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if (!offset || (PAGE_SIZE > 4096)) {
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err = -ENOMEM;
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goto err_unlock;
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}
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@ -1516,7 +1516,7 @@ static int kfd_ioctl_get_dmabuf_info(struct file *filep,
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/* Find a KFD GPU device that supports the get_dmabuf_info query */
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for (i = 0; kfd_topology_enum_kfd_devices(i, &dev) == 0; i++)
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if (dev)
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if (dev && !kfd_devcgroup_check_permission(dev))
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break;
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if (!dev)
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return -EINVAL;
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@ -1538,7 +1538,7 @@ static int kfd_ioctl_get_dmabuf_info(struct file *filep,
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if (xcp_id >= 0)
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args->gpu_id = dmabuf_adev->kfd.dev->nodes[xcp_id]->id;
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else
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args->gpu_id = dmabuf_adev->kfd.dev->nodes[0]->id;
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args->gpu_id = dev->id;
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args->flags = flags;
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/* Copy metadata buffer to user mode */
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@ -2307,7 +2307,7 @@ static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd,
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return -EINVAL;
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}
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offset = pdd->dev->adev->rmmio_remap.bus_addr;
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if (!offset) {
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if (!offset || (PAGE_SIZE > 4096)) {
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pr_err("amdgpu_amdkfd_get_mmio_remap_phys_addr failed\n");
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return -ENOMEM;
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}
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@ -3348,6 +3348,9 @@ static int kfd_mmio_mmap(struct kfd_node *dev, struct kfd_process *process,
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if (vma->vm_end - vma->vm_start != PAGE_SIZE)
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return -EINVAL;
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if (PAGE_SIZE > 4096)
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return -EINVAL;
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address = dev->adev->rmmio_remap.bus_addr;
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vm_flags_set(vma, VM_IO | VM_DONTCOPY | VM_DONTEXPAND | VM_NORESERVE |
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@ -935,7 +935,6 @@ void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm)
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{
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struct kfd_node *node;
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int i;
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int count;
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if (!kfd->init_complete)
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return;
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@ -943,12 +942,10 @@ void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm)
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/* for runtime suspend, skip locking kfd */
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if (!run_pm) {
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mutex_lock(&kfd_processes_mutex);
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count = ++kfd_locked;
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mutex_unlock(&kfd_processes_mutex);
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/* For first KFD device suspend all the KFD processes */
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if (count == 1)
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if (++kfd_locked == 1)
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kfd_suspend_all_processes();
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mutex_unlock(&kfd_processes_mutex);
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}
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for (i = 0; i < kfd->num_nodes; i++) {
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@ -959,7 +956,7 @@ void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm)
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int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm)
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{
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int ret, count, i;
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int ret, i;
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if (!kfd->init_complete)
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return 0;
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@ -973,12 +970,10 @@ int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm)
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/* for runtime resume, skip unlocking kfd */
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if (!run_pm) {
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mutex_lock(&kfd_processes_mutex);
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count = --kfd_locked;
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mutex_unlock(&kfd_processes_mutex);
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WARN_ONCE(count < 0, "KFD suspend / resume ref. error");
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if (count == 0)
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if (--kfd_locked == 0)
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ret = kfd_resume_all_processes();
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WARN_ONCE(kfd_locked < 0, "KFD suspend / resume ref. error");
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mutex_unlock(&kfd_processes_mutex);
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}
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return ret;
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@ -336,7 +336,8 @@ static void event_interrupt_wq_v10(struct kfd_node *dev,
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break;
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}
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kfd_signal_event_interrupt(pasid, context_id0 & 0x7fffff, 23);
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} else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE) {
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} else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE &&
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KFD_DBG_EC_TYPE_IS_PACKET(KFD_DEBUG_CP_BAD_OP_ECODE(context_id0))) {
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kfd_set_dbg_ev_from_interrupt(dev, pasid,
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KFD_DEBUG_DOORBELL_ID(context_id0),
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KFD_EC_MASK(KFD_DEBUG_CP_BAD_OP_ECODE(context_id0)),
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@ -325,7 +325,8 @@ static void event_interrupt_wq_v11(struct kfd_node *dev,
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/* CP */
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if (source_id == SOC15_INTSRC_CP_END_OF_PIPE)
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kfd_signal_event_interrupt(pasid, context_id0, 32);
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else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE)
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else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE &&
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KFD_DBG_EC_TYPE_IS_PACKET(KFD_CTXID0_CP_BAD_OP_ECODE(context_id0)))
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kfd_set_dbg_ev_from_interrupt(dev, pasid,
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KFD_CTXID0_DOORBELL_ID(context_id0),
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KFD_EC_MASK(KFD_CTXID0_CP_BAD_OP_ECODE(context_id0)),
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@ -385,7 +385,8 @@ static void event_interrupt_wq_v9(struct kfd_node *dev,
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break;
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}
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kfd_signal_event_interrupt(pasid, sq_int_data, 24);
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} else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE) {
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} else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE &&
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KFD_DBG_EC_TYPE_IS_PACKET(KFD_DEBUG_CP_BAD_OP_ECODE(context_id0))) {
|
||||
kfd_set_dbg_ev_from_interrupt(dev, pasid,
|
||||
KFD_DEBUG_DOORBELL_ID(context_id0),
|
||||
KFD_EC_MASK(KFD_DEBUG_CP_BAD_OP_ECODE(context_id0)),
|
||||
|
|
|
@ -2978,6 +2978,10 @@ static int dm_resume(void *handle)
|
|||
/* Do mst topology probing after resuming cached state*/
|
||||
drm_connector_list_iter_begin(ddev, &iter);
|
||||
drm_for_each_connector_iter(connector, &iter) {
|
||||
|
||||
if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
|
||||
continue;
|
||||
|
||||
aconnector = to_amdgpu_dm_connector(connector);
|
||||
if (aconnector->dc_link->type != dc_connection_mst_branch ||
|
||||
aconnector->mst_root)
|
||||
|
@ -5760,6 +5764,9 @@ get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
|
|||
&aconnector->base.probed_modes :
|
||||
&aconnector->base.modes;
|
||||
|
||||
if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
|
||||
return NULL;
|
||||
|
||||
if (aconnector->freesync_vid_base.clock != 0)
|
||||
return &aconnector->freesync_vid_base;
|
||||
|
||||
|
@ -8451,6 +8458,9 @@ static void amdgpu_dm_commit_audio(struct drm_device *dev,
|
|||
continue;
|
||||
|
||||
notify:
|
||||
if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
|
||||
continue;
|
||||
|
||||
aconnector = to_amdgpu_dm_connector(connector);
|
||||
|
||||
mutex_lock(&adev->dm.audio_lock);
|
||||
|
|
|
@ -1465,7 +1465,9 @@ static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf,
|
|||
for (i = 0; i < MAX_PIPES; i++) {
|
||||
pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
|
||||
if (pipe_ctx->stream &&
|
||||
pipe_ctx->stream->link == aconnector->dc_link)
|
||||
pipe_ctx->stream->link == aconnector->dc_link &&
|
||||
pipe_ctx->stream->sink &&
|
||||
pipe_ctx->stream->sink == aconnector->dc_sink)
|
||||
break;
|
||||
}
|
||||
|
||||
|
@ -1566,7 +1568,9 @@ static ssize_t dp_dsc_clock_en_write(struct file *f, const char __user *buf,
|
|||
for (i = 0; i < MAX_PIPES; i++) {
|
||||
pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
|
||||
if (pipe_ctx->stream &&
|
||||
pipe_ctx->stream->link == aconnector->dc_link)
|
||||
pipe_ctx->stream->link == aconnector->dc_link &&
|
||||
pipe_ctx->stream->sink &&
|
||||
pipe_ctx->stream->sink == aconnector->dc_sink)
|
||||
break;
|
||||
}
|
||||
|
||||
|
@ -1651,7 +1655,9 @@ static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf,
|
|||
for (i = 0; i < MAX_PIPES; i++) {
|
||||
pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
|
||||
if (pipe_ctx->stream &&
|
||||
pipe_ctx->stream->link == aconnector->dc_link)
|
||||
pipe_ctx->stream->link == aconnector->dc_link &&
|
||||
pipe_ctx->stream->sink &&
|
||||
pipe_ctx->stream->sink == aconnector->dc_sink)
|
||||
break;
|
||||
}
|
||||
|
||||
|
@ -1750,7 +1756,9 @@ static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf,
|
|||
for (i = 0; i < MAX_PIPES; i++) {
|
||||
pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
|
||||
if (pipe_ctx->stream &&
|
||||
pipe_ctx->stream->link == aconnector->dc_link)
|
||||
pipe_ctx->stream->link == aconnector->dc_link &&
|
||||
pipe_ctx->stream->sink &&
|
||||
pipe_ctx->stream->sink == aconnector->dc_sink)
|
||||
break;
|
||||
}
|
||||
|
||||
|
@ -1835,7 +1843,9 @@ static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf,
|
|||
for (i = 0; i < MAX_PIPES; i++) {
|
||||
pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
|
||||
if (pipe_ctx->stream &&
|
||||
pipe_ctx->stream->link == aconnector->dc_link)
|
||||
pipe_ctx->stream->link == aconnector->dc_link &&
|
||||
pipe_ctx->stream->sink &&
|
||||
pipe_ctx->stream->sink == aconnector->dc_sink)
|
||||
break;
|
||||
}
|
||||
|
||||
|
@ -1934,7 +1944,9 @@ static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf,
|
|||
for (i = 0; i < MAX_PIPES; i++) {
|
||||
pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
|
||||
if (pipe_ctx->stream &&
|
||||
pipe_ctx->stream->link == aconnector->dc_link)
|
||||
pipe_ctx->stream->link == aconnector->dc_link &&
|
||||
pipe_ctx->stream->sink &&
|
||||
pipe_ctx->stream->sink == aconnector->dc_sink)
|
||||
break;
|
||||
}
|
||||
|
||||
|
@ -2015,7 +2027,9 @@ static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf,
|
|||
for (i = 0; i < MAX_PIPES; i++) {
|
||||
pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
|
||||
if (pipe_ctx->stream &&
|
||||
pipe_ctx->stream->link == aconnector->dc_link)
|
||||
pipe_ctx->stream->link == aconnector->dc_link &&
|
||||
pipe_ctx->stream->sink &&
|
||||
pipe_ctx->stream->sink == aconnector->dc_sink)
|
||||
break;
|
||||
}
|
||||
|
||||
|
@ -2111,7 +2125,9 @@ static ssize_t dp_dsc_bits_per_pixel_write(struct file *f, const char __user *bu
|
|||
for (i = 0; i < MAX_PIPES; i++) {
|
||||
pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
|
||||
if (pipe_ctx->stream &&
|
||||
pipe_ctx->stream->link == aconnector->dc_link)
|
||||
pipe_ctx->stream->link == aconnector->dc_link &&
|
||||
pipe_ctx->stream->sink &&
|
||||
pipe_ctx->stream->sink == aconnector->dc_sink)
|
||||
break;
|
||||
}
|
||||
|
||||
|
@ -2190,7 +2206,9 @@ static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf,
|
|||
for (i = 0; i < MAX_PIPES; i++) {
|
||||
pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
|
||||
if (pipe_ctx->stream &&
|
||||
pipe_ctx->stream->link == aconnector->dc_link)
|
||||
pipe_ctx->stream->link == aconnector->dc_link &&
|
||||
pipe_ctx->stream->sink &&
|
||||
pipe_ctx->stream->sink == aconnector->dc_sink)
|
||||
break;
|
||||
}
|
||||
|
||||
|
@ -2246,7 +2264,9 @@ static ssize_t dp_dsc_pic_height_read(struct file *f, char __user *buf,
|
|||
for (i = 0; i < MAX_PIPES; i++) {
|
||||
pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
|
||||
if (pipe_ctx->stream &&
|
||||
pipe_ctx->stream->link == aconnector->dc_link)
|
||||
pipe_ctx->stream->link == aconnector->dc_link &&
|
||||
pipe_ctx->stream->sink &&
|
||||
pipe_ctx->stream->sink == aconnector->dc_sink)
|
||||
break;
|
||||
}
|
||||
|
||||
|
@ -2317,7 +2337,9 @@ static ssize_t dp_dsc_chunk_size_read(struct file *f, char __user *buf,
|
|||
for (i = 0; i < MAX_PIPES; i++) {
|
||||
pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
|
||||
if (pipe_ctx->stream &&
|
||||
pipe_ctx->stream->link == aconnector->dc_link)
|
||||
pipe_ctx->stream->link == aconnector->dc_link &&
|
||||
pipe_ctx->stream->sink &&
|
||||
pipe_ctx->stream->sink == aconnector->dc_sink)
|
||||
break;
|
||||
}
|
||||
|
||||
|
@ -2388,7 +2410,9 @@ static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf,
|
|||
for (i = 0; i < MAX_PIPES; i++) {
|
||||
pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
|
||||
if (pipe_ctx->stream &&
|
||||
pipe_ctx->stream->link == aconnector->dc_link)
|
||||
pipe_ctx->stream->link == aconnector->dc_link &&
|
||||
pipe_ctx->stream->sink &&
|
||||
pipe_ctx->stream->sink == aconnector->dc_sink)
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
|
@ -2961,6 +2961,7 @@ static enum bp_result construct_integrated_info(
|
|||
result = get_integrated_info_v2_1(bp, info);
|
||||
break;
|
||||
case 2:
|
||||
case 3:
|
||||
result = get_integrated_info_v2_2(bp, info);
|
||||
break;
|
||||
default:
|
||||
|
|
|
@ -395,6 +395,12 @@ void dcn31_hpo_dp_link_enc_set_throttled_vcp_size(
|
|||
x),
|
||||
25));
|
||||
|
||||
// If y rounds up to integer, carry it over to x.
|
||||
if (y >> 25) {
|
||||
x += 1;
|
||||
y = 0;
|
||||
}
|
||||
|
||||
switch (stream_encoder_inst) {
|
||||
case 0:
|
||||
REG_SET_2(DP_DPHY_SYM32_VC_RATE_CNTL0, 0,
|
||||
|
|
|
@ -226,7 +226,7 @@ static int smu_v13_0_4_system_features_control(struct smu_context *smu, bool en)
|
|||
struct amdgpu_device *adev = smu->adev;
|
||||
int ret = 0;
|
||||
|
||||
if (!en && !adev->in_s0ix) {
|
||||
if (!en && adev->in_s4) {
|
||||
/* Adds a GFX reset as workaround just before sending the
|
||||
* MP1_UNLOAD message to prevent GC/RLC/PMFW from entering
|
||||
* an invalid state.
|
||||
|
|
|
@ -2933,7 +2933,7 @@ int drm_mode_getconnector(struct drm_device *dev, void *data,
|
|||
dev->mode_config.max_width,
|
||||
dev->mode_config.max_height);
|
||||
else
|
||||
drm_dbg_kms(dev, "User-space requested a forced probe on [CONNECTOR:%d:%s] but is not the DRM master, demoting to read-only probe",
|
||||
drm_dbg_kms(dev, "User-space requested a forced probe on [CONNECTOR:%d:%s] but is not the DRM master, demoting to read-only probe\n",
|
||||
connector->base.id, connector->name);
|
||||
}
|
||||
|
||||
|
|
|
@ -75,19 +75,6 @@ struct intel_audio_funcs {
|
|||
struct intel_crtc_state *crtc_state);
|
||||
};
|
||||
|
||||
/* DP N/M table */
|
||||
#define LC_810M 810000
|
||||
#define LC_540M 540000
|
||||
#define LC_270M 270000
|
||||
#define LC_162M 162000
|
||||
|
||||
struct dp_aud_n_m {
|
||||
int sample_rate;
|
||||
int clock;
|
||||
u16 m;
|
||||
u16 n;
|
||||
};
|
||||
|
||||
struct hdmi_aud_ncts {
|
||||
int sample_rate;
|
||||
int clock;
|
||||
|
@ -95,60 +82,6 @@ struct hdmi_aud_ncts {
|
|||
int cts;
|
||||
};
|
||||
|
||||
/* Values according to DP 1.4 Table 2-104 */
|
||||
static const struct dp_aud_n_m dp_aud_n_m[] = {
|
||||
{ 32000, LC_162M, 1024, 10125 },
|
||||
{ 44100, LC_162M, 784, 5625 },
|
||||
{ 48000, LC_162M, 512, 3375 },
|
||||
{ 64000, LC_162M, 2048, 10125 },
|
||||
{ 88200, LC_162M, 1568, 5625 },
|
||||
{ 96000, LC_162M, 1024, 3375 },
|
||||
{ 128000, LC_162M, 4096, 10125 },
|
||||
{ 176400, LC_162M, 3136, 5625 },
|
||||
{ 192000, LC_162M, 2048, 3375 },
|
||||
{ 32000, LC_270M, 1024, 16875 },
|
||||
{ 44100, LC_270M, 784, 9375 },
|
||||
{ 48000, LC_270M, 512, 5625 },
|
||||
{ 64000, LC_270M, 2048, 16875 },
|
||||
{ 88200, LC_270M, 1568, 9375 },
|
||||
{ 96000, LC_270M, 1024, 5625 },
|
||||
{ 128000, LC_270M, 4096, 16875 },
|
||||
{ 176400, LC_270M, 3136, 9375 },
|
||||
{ 192000, LC_270M, 2048, 5625 },
|
||||
{ 32000, LC_540M, 1024, 33750 },
|
||||
{ 44100, LC_540M, 784, 18750 },
|
||||
{ 48000, LC_540M, 512, 11250 },
|
||||
{ 64000, LC_540M, 2048, 33750 },
|
||||
{ 88200, LC_540M, 1568, 18750 },
|
||||
{ 96000, LC_540M, 1024, 11250 },
|
||||
{ 128000, LC_540M, 4096, 33750 },
|
||||
{ 176400, LC_540M, 3136, 18750 },
|
||||
{ 192000, LC_540M, 2048, 11250 },
|
||||
{ 32000, LC_810M, 1024, 50625 },
|
||||
{ 44100, LC_810M, 784, 28125 },
|
||||
{ 48000, LC_810M, 512, 16875 },
|
||||
{ 64000, LC_810M, 2048, 50625 },
|
||||
{ 88200, LC_810M, 1568, 28125 },
|
||||
{ 96000, LC_810M, 1024, 16875 },
|
||||
{ 128000, LC_810M, 4096, 50625 },
|
||||
{ 176400, LC_810M, 3136, 28125 },
|
||||
{ 192000, LC_810M, 2048, 16875 },
|
||||
};
|
||||
|
||||
static const struct dp_aud_n_m *
|
||||
audio_config_dp_get_n_m(const struct intel_crtc_state *crtc_state, int rate)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(dp_aud_n_m); i++) {
|
||||
if (rate == dp_aud_n_m[i].sample_rate &&
|
||||
crtc_state->port_clock == dp_aud_n_m[i].clock)
|
||||
return &dp_aud_n_m[i];
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static const struct {
|
||||
int clock;
|
||||
u32 config;
|
||||
|
@ -386,47 +319,17 @@ hsw_dp_audio_config_update(struct intel_encoder *encoder,
|
|||
const struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
||||
struct i915_audio_component *acomp = i915->display.audio.component;
|
||||
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
|
||||
enum port port = encoder->port;
|
||||
const struct dp_aud_n_m *nm;
|
||||
int rate;
|
||||
u32 tmp;
|
||||
|
||||
rate = acomp ? acomp->aud_sample_rate[port] : 0;
|
||||
nm = audio_config_dp_get_n_m(crtc_state, rate);
|
||||
if (nm)
|
||||
drm_dbg_kms(&i915->drm, "using Maud %u, Naud %u\n", nm->m,
|
||||
nm->n);
|
||||
else
|
||||
drm_dbg_kms(&i915->drm, "using automatic Maud, Naud\n");
|
||||
/* Enable time stamps. Let HW calculate Maud/Naud values */
|
||||
intel_de_rmw(i915, HSW_AUD_CFG(cpu_transcoder),
|
||||
AUD_CONFIG_N_VALUE_INDEX |
|
||||
AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK |
|
||||
AUD_CONFIG_UPPER_N_MASK |
|
||||
AUD_CONFIG_LOWER_N_MASK |
|
||||
AUD_CONFIG_N_PROG_ENABLE,
|
||||
AUD_CONFIG_N_VALUE_INDEX);
|
||||
|
||||
tmp = intel_de_read(i915, HSW_AUD_CFG(cpu_transcoder));
|
||||
tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
|
||||
tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
|
||||
tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
|
||||
tmp |= AUD_CONFIG_N_VALUE_INDEX;
|
||||
|
||||
if (nm) {
|
||||
tmp &= ~AUD_CONFIG_N_MASK;
|
||||
tmp |= AUD_CONFIG_N(nm->n);
|
||||
tmp |= AUD_CONFIG_N_PROG_ENABLE;
|
||||
}
|
||||
|
||||
intel_de_write(i915, HSW_AUD_CFG(cpu_transcoder), tmp);
|
||||
|
||||
tmp = intel_de_read(i915, HSW_AUD_M_CTS_ENABLE(cpu_transcoder));
|
||||
tmp &= ~AUD_CONFIG_M_MASK;
|
||||
tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
|
||||
tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
|
||||
|
||||
if (nm) {
|
||||
tmp |= nm->m;
|
||||
tmp |= AUD_M_CTS_M_VALUE_INDEX;
|
||||
tmp |= AUD_M_CTS_M_PROG_ENABLE;
|
||||
}
|
||||
|
||||
intel_de_write(i915, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp);
|
||||
}
|
||||
|
||||
static void
|
||||
|
|
|
@ -1035,22 +1035,11 @@ parse_lfp_backlight(struct drm_i915_private *i915,
|
|||
panel->vbt.backlight.type = INTEL_BACKLIGHT_DISPLAY_DDI;
|
||||
panel->vbt.backlight.controller = 0;
|
||||
if (i915->display.vbt.version >= 191) {
|
||||
size_t exp_size;
|
||||
const struct lfp_backlight_control_method *method;
|
||||
|
||||
if (i915->display.vbt.version >= 236)
|
||||
exp_size = sizeof(struct bdb_lfp_backlight_data);
|
||||
else if (i915->display.vbt.version >= 234)
|
||||
exp_size = EXP_BDB_LFP_BL_DATA_SIZE_REV_234;
|
||||
else
|
||||
exp_size = EXP_BDB_LFP_BL_DATA_SIZE_REV_191;
|
||||
|
||||
if (get_blocksize(backlight_data) >= exp_size) {
|
||||
const struct lfp_backlight_control_method *method;
|
||||
|
||||
method = &backlight_data->backlight_control[panel_type];
|
||||
panel->vbt.backlight.type = method->type;
|
||||
panel->vbt.backlight.controller = method->controller;
|
||||
}
|
||||
method = &backlight_data->backlight_control[panel_type];
|
||||
panel->vbt.backlight.type = method->type;
|
||||
panel->vbt.backlight.controller = method->controller;
|
||||
}
|
||||
|
||||
panel->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz;
|
||||
|
|
|
@ -897,11 +897,6 @@ struct lfp_brightness_level {
|
|||
u16 reserved;
|
||||
} __packed;
|
||||
|
||||
#define EXP_BDB_LFP_BL_DATA_SIZE_REV_191 \
|
||||
offsetof(struct bdb_lfp_backlight_data, brightness_level)
|
||||
#define EXP_BDB_LFP_BL_DATA_SIZE_REV_234 \
|
||||
offsetof(struct bdb_lfp_backlight_data, brightness_precision_bits)
|
||||
|
||||
struct bdb_lfp_backlight_data {
|
||||
u8 entry_size;
|
||||
struct lfp_backlight_data_entry data[16];
|
||||
|
|
|
@ -8,14 +8,14 @@
|
|||
#include "intel_gt_ccs_mode.h"
|
||||
#include "intel_gt_regs.h"
|
||||
|
||||
void intel_gt_apply_ccs_mode(struct intel_gt *gt)
|
||||
unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt)
|
||||
{
|
||||
int cslice;
|
||||
u32 mode = 0;
|
||||
int first_ccs = __ffs(CCS_MASK(gt));
|
||||
|
||||
if (!IS_DG2(gt->i915))
|
||||
return;
|
||||
return 0;
|
||||
|
||||
/* Build the value for the fixed CCS load balancing */
|
||||
for (cslice = 0; cslice < I915_MAX_CCS; cslice++) {
|
||||
|
@ -35,5 +35,5 @@ void intel_gt_apply_ccs_mode(struct intel_gt *gt)
|
|||
XEHP_CCS_MODE_CSLICE_MASK);
|
||||
}
|
||||
|
||||
intel_uncore_write(gt->uncore, XEHP_CCS_MODE, mode);
|
||||
return mode;
|
||||
}
|
||||
|
|
|
@ -8,6 +8,6 @@
|
|||
|
||||
struct intel_gt;
|
||||
|
||||
void intel_gt_apply_ccs_mode(struct intel_gt *gt);
|
||||
unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt);
|
||||
|
||||
#endif /* __INTEL_GT_CCS_MODE_H__ */
|
||||
|
|
|
@ -2828,6 +2828,7 @@ add_render_compute_tuning_settings(struct intel_gt *gt,
|
|||
static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_list *wal)
|
||||
{
|
||||
struct intel_gt *gt = engine->gt;
|
||||
u32 mode;
|
||||
|
||||
if (!IS_DG2(gt->i915))
|
||||
return;
|
||||
|
@ -2844,7 +2845,8 @@ static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_li
|
|||
* After having disabled automatic load balancing we need to
|
||||
* assign all slices to a single CCS. We will call it CCS mode 1
|
||||
*/
|
||||
intel_gt_apply_ccs_mode(gt);
|
||||
mode = intel_gt_apply_ccs_mode(gt);
|
||||
wa_masked_en(wal, XEHP_CCS_MODE, mode);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
@ -24,6 +24,7 @@
|
|||
#define noinline __attribute__((__noinline__))
|
||||
#define noinline_for_stack __attribute__((__noinline__))
|
||||
#define fallthrough do {} while (0)
|
||||
#define __counted_by(x)
|
||||
|
||||
#define __PASTE(x,y) __CONCAT(x,y)
|
||||
|
||||
|
|
|
@ -424,7 +424,7 @@ typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO{
|
|||
typedef struct _ATOM_PPLIB_STATE_V2
|
||||
{
|
||||
//number of valid dpm levels in this state; Driver uses it to calculate the whole
|
||||
//size of the state: sizeof(ATOM_PPLIB_STATE_V2) + (ucNumDPMLevels - 1) * sizeof(UCHAR)
|
||||
//size of the state: struct_size(ATOM_PPLIB_STATE_V2, clockInfoIndex, ucNumDPMLevels)
|
||||
UCHAR ucNumDPMLevels;
|
||||
|
||||
//a index to the array of nonClockInfos
|
||||
|
@ -432,14 +432,14 @@ typedef struct _ATOM_PPLIB_STATE_V2
|
|||
/**
|
||||
* Driver will read the first ucNumDPMLevels in this array
|
||||
*/
|
||||
UCHAR clockInfoIndex[1];
|
||||
UCHAR clockInfoIndex[] __counted_by(ucNumDPMLevels);
|
||||
} ATOM_PPLIB_STATE_V2;
|
||||
|
||||
typedef struct _StateArray{
|
||||
//how many states we have
|
||||
UCHAR ucNumEntries;
|
||||
|
||||
ATOM_PPLIB_STATE_V2 states[1];
|
||||
ATOM_PPLIB_STATE_V2 states[] __counted_by(ucNumEntries);
|
||||
}StateArray;
|
||||
|
||||
|
||||
|
@ -450,7 +450,7 @@ typedef struct _ClockInfoArray{
|
|||
//sizeof(ATOM_PPLIB_CLOCK_INFO)
|
||||
UCHAR ucEntrySize;
|
||||
|
||||
UCHAR clockInfo[1];
|
||||
UCHAR clockInfo[] __counted_by(ucNumEntries);
|
||||
}ClockInfoArray;
|
||||
|
||||
typedef struct _NonClockInfoArray{
|
||||
|
@ -460,7 +460,7 @@ typedef struct _NonClockInfoArray{
|
|||
//sizeof(ATOM_PPLIB_NONCLOCK_INFO)
|
||||
UCHAR ucEntrySize;
|
||||
|
||||
ATOM_PPLIB_NONCLOCK_INFO nonClockInfo[1];
|
||||
ATOM_PPLIB_NONCLOCK_INFO nonClockInfo[] __counted_by(ucNumEntries);
|
||||
}NonClockInfoArray;
|
||||
|
||||
typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Record
|
||||
|
|
|
@ -92,7 +92,7 @@ int ttm_tt_create(struct ttm_buffer_object *bo, bool zero_alloc)
|
|||
*/
|
||||
if (bdev->pool.use_dma_alloc && cc_platform_has(CC_ATTR_GUEST_MEM_ENCRYPT)) {
|
||||
page_flags |= TTM_TT_FLAG_DECRYPTED;
|
||||
drm_info(ddev, "TT memory decryption enabled.");
|
||||
drm_info_once(ddev, "TT memory decryption enabled.");
|
||||
}
|
||||
|
||||
bo->ttm = bdev->funcs->ttm_tt_create(bo, page_flags);
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue