sync with OpenBSD -current
This commit is contained in:
parent
aaa686b79e
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1093aeaee4
GPG key ID:
F42C07F07E2E35B7
25 changed files with 7769 additions and 280 deletions
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@ -1,7 +1,8 @@
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/* $OpenBSD: if_rge.c,v 1.26 2024/05/24 06:02:56 jsg Exp $ */
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/* $OpenBSD: if_rge.c,v 1.27 2024/06/30 08:13:02 kevlo Exp $ */
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/*
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* Copyright (c) 2019, 2020, 2023 Kevin Lo <kevlo@openbsd.org>
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* Copyright (c) 2019, 2020, 2023, 2024
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* Kevin Lo <kevlo@openbsd.org>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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@ -88,6 +89,7 @@ void rge_ephy_config(struct rge_softc *);
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void rge_ephy_config_mac_cfg3(struct rge_softc *);
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void rge_ephy_config_mac_cfg5(struct rge_softc *);
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int rge_phy_config(struct rge_softc *);
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void rge_phy_config_mac_cfg2_8126(struct rge_softc *);
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void rge_phy_config_mac_cfg3(struct rge_softc *);
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void rge_phy_config_mac_cfg5(struct rge_softc *);
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void rge_phy_config_mcu(struct rge_softc *, uint16_t);
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@ -136,6 +138,8 @@ static const struct {
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RTL8125_MAC_CFG3_MCU
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}, rtl8125_mac_cfg5_mcu[] = {
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RTL8125_MAC_CFG5_MCU
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}, rtl8126_mac_cfg2_mcu[] = {
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RTL8126_MAC_CFG2_MCU
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};
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const struct cfattach rge_ca = {
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@ -148,7 +152,8 @@ struct cfdriver rge_cd = {
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const struct pci_matchid rge_devices[] = {
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{ PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_E3000 },
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{ PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RTL8125 }
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{ PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RTL8125 },
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{ PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RTL8126 }
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};
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int
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@ -239,6 +244,9 @@ rge_attach(struct device *parent, struct device *self, void *aux)
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case 0x64100000:
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sc->rge_type = MAC_CFG5;
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break;
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case 0x64900000:
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sc->rge_type = MAC_CFG2_8126;
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break;
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default:
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printf(": unknown version 0x%08x\n", hwrev);
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return;
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@ -626,7 +634,7 @@ rge_init(struct ifnet *ifp)
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{
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struct rge_softc *sc = ifp->if_softc;
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struct rge_queues *q = sc->sc_queues;
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uint32_t val;
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uint32_t rxconf, val;
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int i, num_miti;
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rge_stop(ifp);
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@ -649,7 +657,6 @@ rge_init(struct ifnet *ifp)
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rge_disable_aspm_clkreq(sc);
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RGE_WRITE_2(sc, RGE_EEE_TXIDLE_TIMER,
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RGE_JUMBO_MTU + ETHER_HDR_LEN + 32);
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RGE_CLRBIT_1(sc, RGE_CFG3, RGE_CFG3_RDY_TO_L23);
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/* Load the addresses of the RX and TX lists into the chip. */
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RGE_WRITE_4(sc, RGE_RXDESC_ADDR_LO,
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@ -662,15 +669,24 @@ rge_init(struct ifnet *ifp)
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RGE_ADDR_HI(q->q_tx.rge_tx_list_map->dm_segs[0].ds_addr));
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/* Set the initial RX and TX configurations. */
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RGE_WRITE_4(sc, RGE_RXCFG,
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(sc->rge_type == MAC_CFG3) ? RGE_RXCFG_CONFIG :
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RGE_RXCFG_CONFIG_8125B);
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if (sc->rge_type == MAC_CFG3)
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rxconf = RGE_RXCFG_CONFIG;
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else if (sc->rge_type == MAC_CFG5)
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rxconf = RGE_RXCFG_CONFIG_8125B;
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else
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rxconf = RGE_RXCFG_CONFIG_8126;
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RGE_WRITE_4(sc, RGE_RXCFG, rxconf);
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RGE_WRITE_4(sc, RGE_TXCFG, RGE_TXCFG_CONFIG);
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val = rge_read_csi(sc, 0x70c) & ~0xff000000;
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rge_write_csi(sc, 0x70c, val | 0x27000000);
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RGE_WRITE_2(sc, 0x0382, 0x221b);
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if (sc->rge_type == MAC_CFG2_8126) {
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/* Disable L1 timeout. */
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val = rge_read_csi(sc, 0x890) & ~0x00000001;
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rge_write_csi(sc, 0x890, val);
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} else
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RGE_WRITE_2(sc, 0x0382, 0x221b);
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RGE_WRITE_1(sc, RGE_RSS_CTRL, 0);
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@ -684,18 +700,23 @@ rge_init(struct ifnet *ifp)
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RGE_MAC_SETBIT(sc, 0xeb58, 0x0001);
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if (sc->rge_type == MAC_CFG2_8126)
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RGE_CLRBIT_1(sc, 0xd8, 0x02);
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val = rge_read_mac_ocp(sc, 0xe614) & ~0x0700;
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if (sc->rge_type == MAC_CFG3)
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rge_write_mac_ocp(sc, 0xe614, val | 0x0300);
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else
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else if (sc->rge_type == MAC_CFG5)
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rge_write_mac_ocp(sc, 0xe614, val | 0x0200);
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else
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rge_write_mac_ocp(sc, 0xe614, val | 0x0400);
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val = rge_read_mac_ocp(sc, 0xe63e) & ~0x0c00;
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rge_write_mac_ocp(sc, 0xe63e, val |
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((fls(sc->sc_nqueues) - 1) & 0x03) << 10);
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RGE_MAC_CLRBIT(sc, 0xe63e, 0x0030);
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if (sc->rge_type == MAC_CFG3)
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if (sc->rge_type != MAC_CFG5)
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RGE_MAC_SETBIT(sc, 0xe63e, 0x0020);
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RGE_MAC_CLRBIT(sc, 0xc0b4, 0x0001);
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@ -734,7 +755,10 @@ rge_init(struct ifnet *ifp)
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/* Disable EEE plus. */
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RGE_MAC_CLRBIT(sc, 0xe080, 0x0002);
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RGE_MAC_CLRBIT(sc, 0xea1c, 0x0004);
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if (sc->rge_type == MAC_CFG2_8126)
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RGE_MAC_CLRBIT(sc, 0xea1c, 0x0304);
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else
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RGE_MAC_CLRBIT(sc, 0xea1c, 0x0004);
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RGE_MAC_SETBIT(sc, 0xeb54, 0x0001);
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DELAY(1);
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@ -742,8 +766,8 @@ rge_init(struct ifnet *ifp)
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RGE_CLRBIT_2(sc, 0x1880, 0x0030);
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/* Config interrupt type for RTL8125B. */
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if (sc->rge_type == MAC_CFG5)
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/* Config interrupt type for RTL8125B/RTL8126. */
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if (sc->rge_type != MAC_CFG3)
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RGE_CLRBIT_1(sc, RGE_INT_CFG0, RGE_INT_CFG0_EN);
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/* Clear timer interrupts. */
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@ -879,26 +903,31 @@ rge_ifmedia_upd(struct ifnet *ifp)
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/* Disable Gigabit Lite. */
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RGE_PHY_CLRBIT(sc, 0xa428, 0x0200);
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RGE_PHY_CLRBIT(sc, 0xa5ea, 0x0001);
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if (sc->rge_type == MAC_CFG2_8126)
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RGE_PHY_CLRBIT(sc, 0xa5ea, 0x0002);
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val = rge_read_phy_ocp(sc, 0xa5d4);
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val &= ~RGE_ADV_2500TFDX;
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if (sc->rge_type == MAC_CFG2_8126)
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val &= ~RGE_ADV_5000TFDX;
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anar = ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10;
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gig = GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX;
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anar = gig = 0;
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switch (IFM_SUBTYPE(ifm->ifm_media)) {
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case IFM_AUTO:
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anar = ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10;
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gig = GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX;
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val |= RGE_ADV_2500TFDX;
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val |= (sc->rge_type != MAC_CFG2_8126) ?
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RGE_ADV_2500TFDX : (RGE_ADV_2500TFDX | RGE_ADV_5000TFDX);
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break;
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case IFM_5000_T:
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val |= RGE_ADV_5000TFDX;
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ifp->if_baudrate = IF_Gbps(5);
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break;
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case IFM_2500_T:
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anar = ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10;
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gig = GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX;
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val |= RGE_ADV_2500TFDX;
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ifp->if_baudrate = IF_Mbps(2500);
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break;
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case IFM_1000_T:
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anar = ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10;
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gig = GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX;
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ifp->if_baudrate = IF_Gbps(1);
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break;
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case IFM_100_TX:
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@ -947,7 +976,7 @@ rge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
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status = RGE_READ_2(sc, RGE_PHYSTAT);
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if ((status & RGE_PHYSTAT_FDX) ||
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(status & RGE_PHYSTAT_2500MBPS))
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(status & (RGE_PHYSTAT_2500MBPS | RGE_PHYSTAT_5000MBPS)))
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ifmr->ifm_active |= IFM_FDX;
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else
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ifmr->ifm_active |= IFM_HDX;
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@ -960,6 +989,8 @@ rge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
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ifmr->ifm_active |= IFM_1000_T;
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else if (status & RGE_PHYSTAT_2500MBPS)
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ifmr->ifm_active |= IFM_2500_T;
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else if (status & RGE_PHYSTAT_5000MBPS)
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ifmr->ifm_active |= IFM_5000_T;
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}
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}
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@ -1394,10 +1425,12 @@ rge_reset(struct rge_softc *sc)
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DELAY(2000);
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RGE_SETBIT_1(sc, RGE_CMD, RGE_CMD_STOPREQ);
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for (i = 0; i < 20; i++) {
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DELAY(10);
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if (!(RGE_READ_1(sc, RGE_CMD) & RGE_CMD_STOPREQ))
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break;
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if (sc->rge_type != MAC_CFG2_8126) {
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for (i = 0; i < 20; i++) {
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DELAY(10);
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if (!(RGE_READ_1(sc, RGE_CMD) & RGE_CMD_STOPREQ))
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break;
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}
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}
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for (i = 0; i < 3000; i++) {
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@ -1522,7 +1555,7 @@ rge_ephy_config(struct rge_softc *sc)
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rge_ephy_config_mac_cfg5(sc);
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break;
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default:
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break; /* Can't happen. */
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break; /* Nothing to do. */
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}
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}
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@ -1576,7 +1609,10 @@ rge_phy_config(struct rge_softc *sc)
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rge_write_phy(sc, 0, MII_100T2CR,
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rge_read_phy(sc, 0, MII_100T2CR) &
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~(GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX));
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RGE_PHY_CLRBIT(sc, 0xa5d4, RGE_ADV_2500TFDX);
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if (sc->rge_type == MAC_CFG2_8126)
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RGE_PHY_CLRBIT(sc, 0xa5d4, RGE_ADV_2500TFDX | RGE_ADV_5000TFDX);
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else
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RGE_PHY_CLRBIT(sc, 0xa5d4, RGE_ADV_2500TFDX);
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rge_write_phy(sc, 0, MII_BMCR, BMCR_RESET | BMCR_AUTOEN |
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BMCR_STARTNEG);
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for (i = 0; i < 2500; i++) {
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@ -1594,6 +1630,9 @@ rge_phy_config(struct rge_softc *sc)
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sc->rge_mcodever = rge_read_phy_ocp(sc, 0xa438);
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switch (sc->rge_type) {
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case MAC_CFG2_8126:
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rge_phy_config_mac_cfg2_8126(sc);
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break;
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case MAC_CFG3:
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rge_phy_config_mac_cfg3(sc);
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break;
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@ -1611,23 +1650,305 @@ rge_phy_config(struct rge_softc *sc)
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if (sc->rge_type == MAC_CFG3) {
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RGE_MAC_CLRBIT(sc, 0xeb62, 0x0006);
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RGE_PHY_CLRBIT(sc, 0xa432, 0x0010);
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}
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} else if (sc->rge_type == MAC_CFG5)
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RGE_PHY_SETBIT(sc, 0xa432, 0x0010);
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RGE_PHY_CLRBIT(sc, 0xa5d0, 0x0006);
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RGE_PHY_CLRBIT(sc, 0xa6d4, 0x0001);
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if (sc->rge_type == MAC_CFG2_8126)
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RGE_PHY_CLRBIT(sc, 0xa6d4, 0x0002);
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RGE_PHY_CLRBIT(sc, 0xa6d8, 0x0010);
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RGE_PHY_CLRBIT(sc, 0xa428, 0x0080);
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RGE_PHY_CLRBIT(sc, 0xa4a2, 0x0200);
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/* Advanced EEE. */
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rge_patch_phy_mcu(sc, 1);
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/* Disable advanced EEE. */
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RGE_MAC_CLRBIT(sc, 0xe052, 0x0001);
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RGE_PHY_CLRBIT(sc, 0xa442, 0x3000);
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RGE_PHY_CLRBIT(sc, 0xa430, 0x8000);
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rge_patch_phy_mcu(sc, 0);
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return (0);
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}
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void
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rge_phy_config_mac_cfg2_8126(struct rge_softc *sc)
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{
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uint16_t val;
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int i;
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static const uint16_t mac_cfg2_a438_value[] =
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{ 0x0044, 0x00a8, 0x00d6, 0x00ec, 0x00f6, 0x00fc, 0x00fe,
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0x00fe, 0x00bc, 0x0058, 0x002a, 0x003f, 0x3f02, 0x023c,
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0x3b0a, 0x1c00, 0x0000, 0x0000, 0x0000, 0x0000 };
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static const uint16_t mac_cfg2_b87e_value[] =
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{ 0x03ed, 0x03ff, 0x0009, 0x03fe, 0x000b, 0x0021, 0x03f7,
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0x03b8, 0x03e0, 0x0049, 0x0049, 0x03e0, 0x03b8, 0x03f7,
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0x0021, 0x000b, 0x03fe, 0x0009, 0x03ff, 0x03ed, 0x000e,
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0x03fe, 0x03ed, 0x0006, 0x001a, 0x03f1, 0x03d8, 0x0023,
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0x0054, 0x0322, 0x00dd, 0x03ab, 0x03dc, 0x0027, 0x000e,
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0x03e5, 0x03f9, 0x0012, 0x0001, 0x03f1 };
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rge_phy_config_mcu(sc, RGE_MAC_CFG2_8126_MCODE_VER);
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RGE_PHY_SETBIT(sc, 0xa442, 0x0800);
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rge_write_phy_ocp(sc, 0xa436, 0x80bf);
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val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
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rge_write_phy_ocp(sc, 0xa438, val | 0xed00);
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rge_write_phy_ocp(sc, 0xa436, 0x80cd);
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val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
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rge_write_phy_ocp(sc, 0xa438, val | 0x1000);
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rge_write_phy_ocp(sc, 0xa436, 0x80d1);
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val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
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rge_write_phy_ocp(sc, 0xa438, val | 0xc800);
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rge_write_phy_ocp(sc, 0xa436, 0x80d4);
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val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
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rge_write_phy_ocp(sc, 0xa438, val | 0xc800);
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rge_write_phy_ocp(sc, 0xa436, 0x80e1);
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rge_write_phy_ocp(sc, 0xa438, 0x10cc);
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rge_write_phy_ocp(sc, 0xa436, 0x80e5);
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rge_write_phy_ocp(sc, 0xa438, 0x4f0c);
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rge_write_phy_ocp(sc, 0xa436, 0x8387);
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val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
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rge_write_phy_ocp(sc, 0xa438, val | 0x4700);
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val = rge_read_phy_ocp(sc, 0xa80c) & ~0x00c0;
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rge_write_phy_ocp(sc, 0xa80c, val | 0x0080);
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RGE_PHY_CLRBIT(sc, 0xac90, 0x0010);
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RGE_PHY_CLRBIT(sc, 0xad2c, 0x8000);
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rge_write_phy_ocp(sc, 0xb87c, 0x8321);
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val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
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rge_write_phy_ocp(sc, 0xb87e, val | 0x1100);
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RGE_PHY_SETBIT(sc, 0xacf8, 0x000c);
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rge_write_phy_ocp(sc, 0xa436, 0x8183);
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val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
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rge_write_phy_ocp(sc, 0xa438, val | 0x5900);
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RGE_PHY_SETBIT(sc, 0xad94, 0x0020);
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RGE_PHY_CLRBIT(sc, 0xa654, 0x0800);
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RGE_PHY_SETBIT(sc, 0xb648, 0x4000);
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rge_write_phy_ocp(sc, 0xb87c, 0x839e);
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val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
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rge_write_phy_ocp(sc, 0xb87e, val | 0x2f00);
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rge_write_phy_ocp(sc, 0xb87c, 0x83f2);
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val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
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rge_write_phy_ocp(sc, 0xb87e, val | 0x0800);
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RGE_PHY_SETBIT(sc, 0xada0, 0x0002);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x80f3);
|
||||
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
|
||||
rge_write_phy_ocp(sc, 0xb87e, val | 0x9900);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x8126);
|
||||
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
|
||||
rge_write_phy_ocp(sc, 0xb87e, val | 0xc100);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x893a);
|
||||
rge_write_phy_ocp(sc, 0xb87e, 0x8080);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x8647);
|
||||
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
|
||||
rge_write_phy_ocp(sc, 0xb87e, val | 0xe600);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x862c);
|
||||
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
|
||||
rge_write_phy_ocp(sc, 0xb87e, val | 0x1200);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x864a);
|
||||
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
|
||||
rge_write_phy_ocp(sc, 0xb87e, val | 0xe600);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x80a0);
|
||||
rge_write_phy_ocp(sc, 0xb87e, 0xbcbc);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x805e);
|
||||
rge_write_phy_ocp(sc, 0xb87e, 0xbcbc);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x8056);
|
||||
rge_write_phy_ocp(sc, 0xb87e, 0x3077);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x8058);
|
||||
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
|
||||
rge_write_phy_ocp(sc, 0xb87e, val | 0x5a00);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x8098);
|
||||
rge_write_phy_ocp(sc, 0xb87e, 0x3077);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x809a);
|
||||
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
|
||||
rge_write_phy_ocp(sc, 0xb87e, val | 0x5a00);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x8052);
|
||||
rge_write_phy_ocp(sc, 0xb87e, 0x3733);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x8094);
|
||||
rge_write_phy_ocp(sc, 0xb87e, 0x3733);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x807f);
|
||||
rge_write_phy_ocp(sc, 0xb87e, 0x7c75);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x803d);
|
||||
rge_write_phy_ocp(sc, 0xb87e, 0x7c75);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x8036);
|
||||
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
|
||||
rge_write_phy_ocp(sc, 0xb87e, val | 0x3000);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x8078);
|
||||
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
|
||||
rge_write_phy_ocp(sc, 0xb87e, val | 0x3000);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x8031);
|
||||
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
|
||||
rge_write_phy_ocp(sc, 0xb87e, val | 0x3300);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x8073);
|
||||
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
|
||||
rge_write_phy_ocp(sc, 0xb87e, val | 0x3300);
|
||||
val = rge_read_phy_ocp(sc, 0xae06) & ~0xfc00;
|
||||
rge_write_phy_ocp(sc, 0xae06, val | 0x7c00);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x89D1);
|
||||
rge_write_phy_ocp(sc, 0xb87e, 0x0004);
|
||||
rge_write_phy_ocp(sc, 0xa436, 0x8fbd);
|
||||
val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
|
||||
rge_write_phy_ocp(sc, 0xa438, val | 0x0a00);
|
||||
rge_write_phy_ocp(sc, 0xa436, 0x8fbe);
|
||||
rge_write_phy_ocp(sc, 0xa438, 0x0d09);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x89cd);
|
||||
rge_write_phy_ocp(sc, 0xb87e, 0x0f0f);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x89cf);
|
||||
rge_write_phy_ocp(sc, 0xb87e, 0x0f0f);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x83a4);
|
||||
rge_write_phy_ocp(sc, 0xb87e, 0x6600);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x83a6);
|
||||
rge_write_phy_ocp(sc, 0xb87e, 0x6601);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x83c0);
|
||||
rge_write_phy_ocp(sc, 0xb87e, 0x6600);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x83c2);
|
||||
rge_write_phy_ocp(sc, 0xb87e, 0x6601);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x8414);
|
||||
rge_write_phy_ocp(sc, 0xb87e, 0x6600);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x8416);
|
||||
rge_write_phy_ocp(sc, 0xb87e, 0x6601);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x83f8);
|
||||
rge_write_phy_ocp(sc, 0xb87e, 0x6600);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x83fa);
|
||||
rge_write_phy_ocp(sc, 0xb87e, 0x6601);
|
||||
|
||||
rge_patch_phy_mcu(sc, 1);
|
||||
val = rge_read_phy_ocp(sc, 0xbd96) & ~0x1f00;
|
||||
rge_write_phy_ocp(sc, 0xbd96, val | 0x1000);
|
||||
val = rge_read_phy_ocp(sc, 0xbf1c) & ~0x0007;
|
||||
rge_write_phy_ocp(sc, 0xbf1c, val | 0x0007);
|
||||
RGE_PHY_CLRBIT(sc, 0xbfbe, 0x8000);
|
||||
val = rge_read_phy_ocp(sc, 0xbf40) & ~0x0380;
|
||||
rge_write_phy_ocp(sc, 0xbf40, val | 0x0280);
|
||||
val = rge_read_phy_ocp(sc, 0xbf90) & ~0x0080;
|
||||
rge_write_phy_ocp(sc, 0xbf90, val | 0x0060);
|
||||
val = rge_read_phy_ocp(sc, 0xbf90) & ~0x0010;
|
||||
rge_write_phy_ocp(sc, 0xbf90, val | 0x000c);
|
||||
rge_patch_phy_mcu(sc, 0);
|
||||
|
||||
rge_write_phy_ocp(sc, 0xa436, 0x843b);
|
||||
val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
|
||||
rge_write_phy_ocp(sc, 0xa438, val | 0x2000);
|
||||
rge_write_phy_ocp(sc, 0xa436, 0x843d);
|
||||
val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
|
||||
rge_write_phy_ocp(sc, 0xa438, val | 0x2000);
|
||||
RGE_PHY_CLRBIT(sc, 0xb516, 0x007f);
|
||||
RGE_PHY_CLRBIT(sc, 0xbf80, 0x0030);
|
||||
|
||||
rge_write_phy_ocp(sc, 0xa436, 0x8188);
|
||||
for (i = 0; i < 11; i++)
|
||||
rge_write_phy_ocp(sc, 0xa438, mac_cfg2_a438_value[i]);
|
||||
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x8015);
|
||||
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
|
||||
rge_write_phy_ocp(sc, 0xb87e, val | 0x0800);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x8ffd);
|
||||
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
|
||||
rge_write_phy_ocp(sc, 0xb87e, val | 0);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x8fff);
|
||||
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
|
||||
rge_write_phy_ocp(sc, 0xb87e, val | 0x7f00);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x8ffb);
|
||||
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
|
||||
rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x8fe9);
|
||||
rge_write_phy_ocp(sc, 0xb87e, 0x0002);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x8fef);
|
||||
rge_write_phy_ocp(sc, 0xb87e, 0x00a5);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x8ff1);
|
||||
rge_write_phy_ocp(sc, 0xb87e, 0x0106);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x8fe1);
|
||||
rge_write_phy_ocp(sc, 0xb87e, 0x0102);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x8fe3);
|
||||
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
|
||||
rge_write_phy_ocp(sc, 0xb87e, val | 0x0400);
|
||||
RGE_PHY_SETBIT(sc, 0xa654, 0x0800);
|
||||
RGE_PHY_CLRBIT(sc, 0xa654, 0x0003);
|
||||
rge_write_phy_ocp(sc, 0xac3a, 0x5851);
|
||||
val = rge_read_phy_ocp(sc, 0xac3c) & ~0xd000;
|
||||
rge_write_phy_ocp(sc, 0xac3c, val | 0x2000);
|
||||
val = rge_read_phy_ocp(sc, 0xac42) & ~0x0200;
|
||||
rge_write_phy_ocp(sc, 0xac42, val | 0x01c0);
|
||||
RGE_PHY_CLRBIT(sc, 0xac3e, 0xe000);
|
||||
RGE_PHY_CLRBIT(sc, 0xac42, 0x0038);
|
||||
val = rge_read_phy_ocp(sc, 0xac42) & ~0x0002;
|
||||
rge_write_phy_ocp(sc, 0xac42, val | 0x0005);
|
||||
rge_write_phy_ocp(sc, 0xac1a, 0x00db);
|
||||
rge_write_phy_ocp(sc, 0xade4, 0x01b5);
|
||||
RGE_PHY_CLRBIT(sc, 0xad9c, 0x0c00);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x814b);
|
||||
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
|
||||
rge_write_phy_ocp(sc, 0xb87e, val | 0x1100);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x814d);
|
||||
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
|
||||
rge_write_phy_ocp(sc, 0xb87e, val | 0x1100);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x814f);
|
||||
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
|
||||
rge_write_phy_ocp(sc, 0xb87e, val | 0x0b00);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x8142);
|
||||
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
|
||||
rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x8144);
|
||||
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
|
||||
rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x8150);
|
||||
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
|
||||
rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x8118);
|
||||
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
|
||||
rge_write_phy_ocp(sc, 0xb87e, val | 0x0700);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x811a);
|
||||
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
|
||||
rge_write_phy_ocp(sc, 0xb87e, val | 0x0700);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x811c);
|
||||
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
|
||||
rge_write_phy_ocp(sc, 0xb87e, val | 0x0500);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x810f);
|
||||
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
|
||||
rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x8111);
|
||||
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
|
||||
rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x811d);
|
||||
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
|
||||
rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
|
||||
RGE_PHY_SETBIT(sc, 0xac36, 0x1000);
|
||||
RGE_PHY_CLRBIT(sc, 0xad1c, 0x0100);
|
||||
val = rge_read_phy_ocp(sc, 0xade8) & ~0xffc0;
|
||||
rge_write_phy_ocp(sc, 0xade8, val | 0x1400);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x864b);
|
||||
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
|
||||
rge_write_phy_ocp(sc, 0xb87e, val | 0x9d00);
|
||||
|
||||
rge_write_phy_ocp(sc, 0xa436, 0x8f97);
|
||||
for (; i < nitems(mac_cfg2_a438_value); i++)
|
||||
rge_write_phy_ocp(sc, 0xa438, mac_cfg2_a438_value[i]);
|
||||
|
||||
RGE_PHY_SETBIT(sc, 0xad9c, 0x0020);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x8122);
|
||||
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
|
||||
rge_write_phy_ocp(sc, 0xb87e, val | 0x0c00);
|
||||
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x82c8);
|
||||
for (i = 0; i < 20; i++)
|
||||
rge_write_phy_ocp(sc, 0xb87e, mac_cfg2_b87e_value[i]);
|
||||
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x80ef);
|
||||
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
|
||||
rge_write_phy_ocp(sc, 0xb87e, val | 0x0c00);
|
||||
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x82a0);
|
||||
for (; i < nitems(mac_cfg2_b87e_value); i++)
|
||||
rge_write_phy_ocp(sc, 0xb87e, mac_cfg2_b87e_value[i]);
|
||||
|
||||
rge_write_phy_ocp(sc, 0xa436, 0x8018);
|
||||
RGE_PHY_SETBIT(sc, 0xa438, 0x2000);
|
||||
rge_write_phy_ocp(sc, 0xb87c, 0x8fe4);
|
||||
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
|
||||
rge_write_phy_ocp(sc, 0xb87e, val | 0);
|
||||
val = rge_read_phy_ocp(sc, 0xb54c) & ~0xffc0;
|
||||
rge_write_phy_ocp(sc, 0xb54c, val | 0x3700);
|
||||
}
|
||||
|
||||
void
|
||||
rge_phy_config_mac_cfg3(struct rge_softc *sc)
|
||||
{
|
||||
|
|
@ -1784,6 +2105,12 @@ rge_phy_config_mcu(struct rge_softc *sc, uint16_t mcode_version)
|
|||
rtl8125_mac_cfg5_mcu[i].reg,
|
||||
rtl8125_mac_cfg5_mcu[i].val);
|
||||
}
|
||||
} else if (sc->rge_type == MAC_CFG2_8126) {
|
||||
for (i = 0; i < nitems(rtl8126_mac_cfg2_mcu); i++) {
|
||||
rge_write_phy_ocp(sc,
|
||||
rtl8126_mac_cfg2_mcu[i].reg,
|
||||
rtl8126_mac_cfg2_mcu[i].val);
|
||||
}
|
||||
}
|
||||
|
||||
rge_patch_phy_mcu(sc, 0);
|
||||
|
|
@ -1881,7 +2208,8 @@ rge_hw_init(struct rge_softc *sc)
|
|||
}
|
||||
|
||||
/* Disable PHY power saving. */
|
||||
rge_disable_phy_ocp_pwrsave(sc);
|
||||
if (sc->rge_type == MAC_CFG3)
|
||||
rge_disable_phy_ocp_pwrsave(sc);
|
||||
|
||||
/* Set PCIe uncorrectable error status. */
|
||||
rge_write_csi(sc, 0x108,
|
||||
|
|
@ -1951,6 +2279,12 @@ rge_add_media_types(struct rge_softc *sc)
|
|||
ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
|
||||
ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_2500_T, 0, NULL);
|
||||
ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_2500_T | IFM_FDX, 0, NULL);
|
||||
|
||||
if (sc->rge_type == MAC_CFG2_8126) {
|
||||
ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_5000_T, 0, NULL);
|
||||
ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_5000_T | IFM_FDX,
|
||||
0, NULL);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
|
|
@ -1972,7 +2306,10 @@ void
|
|||
rge_disable_aspm_clkreq(struct rge_softc *sc)
|
||||
{
|
||||
RGE_SETBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG);
|
||||
RGE_CLRBIT_1(sc, RGE_CFG2, RGE_CFG2_CLKREQ_EN);
|
||||
if (sc->rge_type == MAC_CFG2_8126)
|
||||
RGE_CLRBIT_1(sc, RGE_INT_CFG0, 0x08);
|
||||
else
|
||||
RGE_CLRBIT_1(sc, RGE_CFG2, RGE_CFG2_CLKREQ_EN);
|
||||
RGE_CLRBIT_1(sc, RGE_CFG5, RGE_CFG5_PME_STS);
|
||||
RGE_CLRBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG);
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue