sync with OpenBSD -current
This commit is contained in:
parent
2d0895064a
commit
0d235ae71d
GPG key ID:
F42C07F07E2E35B7
70 changed files with 1715 additions and 502 deletions
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@ -1,4 +1,4 @@
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/* $OpenBSD: fms.c,v 1.38 2024/05/24 06:02:53 jsg Exp $ */
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/* $OpenBSD: fms.c,v 1.39 2024/06/09 05:18:12 jsg Exp $ */
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/* $NetBSD: fms.c,v 1.5.4.1 2000/06/30 16:27:50 simonb Exp $ */
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/*-
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@ -118,9 +118,6 @@ int fms_read_codec(void *, u_int8_t, u_int16_t *);
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int fms_write_codec(void *, u_int8_t, u_int16_t);
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void fms_reset_codec(void *);
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int fms_allocmem(struct fms_softc *, size_t, size_t,
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struct fms_dma *);
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int
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fms_match(struct device *parent, void *match, void *aux)
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{
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@ -31,7 +31,7 @@
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*******************************************************************************/
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/* $OpenBSD: if_em_hw.h,v 1.94 2024/05/13 01:15:51 jsg Exp $ */
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/* $OpenBSD: if_em_hw.h,v 1.95 2024/06/09 05:18:12 jsg Exp $ */
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/* $FreeBSD: if_em_hw.h,v 1.15 2005/05/26 23:32:02 tackerman Exp $ */
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/* if_em_hw.h
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@ -408,8 +408,6 @@ struct em_host_mng_dhcp_cookie{
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};
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int32_t em_read_part_num(struct em_hw *hw, uint32_t *part_num);
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int32_t em_mng_write_dhcp_info(struct em_hw *hw, uint8_t *buffer,
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uint16_t length);
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boolean_t em_check_mng_mode(struct em_hw *hw);
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boolean_t em_enable_tx_pkt_filtering(struct em_hw *hw);
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int32_t em_read_eeprom(struct em_hw *hw, uint16_t reg, uint16_t words, uint16_t *data);
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@ -1,4 +1,4 @@
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/* $OpenBSD: if_vmx.c,v 1.86 2024/05/21 19:49:06 jan Exp $ */
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/* $OpenBSD: if_vmx.c,v 1.87 2024/06/07 08:44:25 jan Exp $ */
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/*
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* Copyright (c) 2013 Tsubai Masanari
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@ -114,6 +114,8 @@ struct vmxnet3_comp_ring {
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};
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u_int next;
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u_int32_t gen;
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struct mbuf *sendmp;
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struct mbuf *lastmp;
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};
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struct vmxnet3_txqueue {
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@ -160,6 +162,7 @@ struct vmxnet3_softc {
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struct vmxnet3_queue *sc_q;
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struct intrmap *sc_intrmap;
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u_int sc_vrrs;
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struct vmxnet3_driver_shared *sc_ds;
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u_int8_t *sc_mcast;
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struct vmxnet3_upt1_rss_conf *sc_rss;
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@ -170,7 +173,7 @@ struct vmxnet3_softc {
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#endif
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};
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#define JUMBO_LEN (1024 * 9)
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#define JUMBO_LEN ((16 * 1024) - 1)
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#define DMAADDR(map) ((map)->dm_segs[0].ds_addr)
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#define READ_BAR0(sc, reg) bus_space_read_4((sc)->sc_iot0, (sc)->sc_ioh0, reg)
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@ -273,15 +276,21 @@ vmxnet3_attach(struct device *parent, struct device *self, void *aux)
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return;
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}
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/* Vmxnet3 Revision Report and Selection */
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ver = READ_BAR1(sc, VMXNET3_BAR1_VRRS);
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if ((ver & 0x1) == 0) {
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if (ISSET(ver, 0x2)) {
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sc->sc_vrrs = 2;
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} else if (ISSET(ver, 0x1)) {
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sc->sc_vrrs = 1;
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} else {
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printf(": unsupported hardware version 0x%x\n", ver);
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return;
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}
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WRITE_BAR1(sc, VMXNET3_BAR1_VRRS, 1);
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WRITE_BAR1(sc, VMXNET3_BAR1_VRRS, sc->sc_vrrs);
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/* UPT Version Report and Selection */
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ver = READ_BAR1(sc, VMXNET3_BAR1_UVRS);
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if ((ver & 0x1) == 0) {
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if (!ISSET(ver, 0x1)) {
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printf(": incompatible UPT version 0x%x\n", ver);
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return;
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}
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@ -410,6 +419,11 @@ vmxnet3_attach(struct device *parent, struct device *self, void *aux)
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ifp->if_capabilities |= IFCAP_TSOv4 | IFCAP_TSOv6;
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if (sc->sc_vrrs == 2) {
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ifp->if_xflags |= IFXF_LRO;
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ifp->if_capabilities |= IFCAP_LRO;
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}
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#if NVLAN > 0
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if (sc->sc_ds->upt_features & UPT1_F_VLAN)
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ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING;
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@ -704,6 +718,10 @@ vmxnet3_rxfill(struct vmxnet3_rxring *ring)
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uint32_t rgen;
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uint32_t type = htole32(VMXNET3_BTYPE_HEAD << VMXNET3_RX_BTYPE_S);
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/* Second ring just contains packet bodies. */
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if (ring->rid == 1)
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type = htole32(VMXNET3_BTYPE_BODY << VMXNET3_RX_BTYPE_S);
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MUTEX_ASSERT_LOCKED(&ring->mtx);
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slots = if_rxr_get(&ring->rxr, NRXDESC);
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@ -781,17 +799,17 @@ vmxnet3_rxinit(struct vmxnet3_softc *sc, struct vmxnet3_rxqueue *rq)
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VMX_DMA_LEN(&ring->dmamem));
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bus_dmamap_sync(sc->sc_dmat, VMX_DMA_MAP(&ring->dmamem),
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0, VMX_DMA_LEN(&ring->dmamem), BUS_DMASYNC_PREWRITE);
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}
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/* XXX only fill ring 0 */
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ring = &rq->cmd_ring[0];
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mtx_enter(&ring->mtx);
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vmxnet3_rxfill(ring);
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mtx_leave(&ring->mtx);
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mtx_enter(&ring->mtx);
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vmxnet3_rxfill(ring);
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mtx_leave(&ring->mtx);
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}
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comp_ring = &rq->comp_ring;
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comp_ring->next = 0;
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comp_ring->gen = VMX_RXC_GEN;
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comp_ring->sendmp = NULL;
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comp_ring->lastmp = NULL;
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memset(VMX_DMA_KVA(&comp_ring->dmamem), 0,
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VMX_DMA_LEN(&comp_ring->dmamem));
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@ -1074,9 +1092,9 @@ vmxnet3_rxintr(struct vmxnet3_softc *sc, struct vmxnet3_rxqueue *rq)
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struct mbuf_list ml = MBUF_LIST_INITIALIZER();
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struct mbuf *m;
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bus_dmamap_t map;
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unsigned int idx, len;
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unsigned int idx;
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unsigned int next, rgen;
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unsigned int done = 0;
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unsigned int rid, done[2] = {0, 0};
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next = comp_ring->next;
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rgen = comp_ring->gen;
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@ -1096,11 +1114,14 @@ vmxnet3_rxintr(struct vmxnet3_softc *sc, struct vmxnet3_rxqueue *rq)
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idx = letoh32((rxcd->rxc_word0 >> VMXNET3_RXC_IDX_S) &
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VMXNET3_RXC_IDX_M);
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if (letoh32((rxcd->rxc_word0 >> VMXNET3_RXC_QID_S) &
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VMXNET3_RXC_QID_M) < sc->sc_nqueues)
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ring = &rq->cmd_ring[0];
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rid = 0;
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else
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ring = &rq->cmd_ring[1];
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rid = 1;
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ring = &rq->cmd_ring[rid];
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m = ring->m[idx];
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KASSERT(m != NULL);
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@ -1111,31 +1132,62 @@ vmxnet3_rxintr(struct vmxnet3_softc *sc, struct vmxnet3_rxqueue *rq)
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BUS_DMASYNC_POSTREAD);
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bus_dmamap_unload(sc->sc_dmat, map);
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done++;
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done[rid]++;
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/*
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* A receive descriptor of type 4 which is flaged as start of
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* packet, contains the number of TCP segment of an LRO packet.
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*/
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if (letoh32((rxcd->rxc_word3 & VMXNET3_RXC_TYPE_M) >>
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VMXNET3_RXC_TYPE_S) == 4 &&
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ISSET(rxcd->rxc_word0, VMXNET3_RXC_SOP)) {
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m->m_pkthdr.ph_mss = letoh32(rxcd->rxc_word1 &
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VMXNET3_RXC_SEG_CNT_M);
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}
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m->m_len = letoh32((rxcd->rxc_word2 >> VMXNET3_RXC_LEN_S) &
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VMXNET3_RXC_LEN_M);
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if (comp_ring->sendmp == NULL) {
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comp_ring->sendmp = comp_ring->lastmp = m;
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comp_ring->sendmp->m_pkthdr.len = 0;
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} else {
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CLR(m->m_flags, M_PKTHDR);
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comp_ring->lastmp->m_next = m;
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comp_ring->lastmp = m;
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}
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comp_ring->sendmp->m_pkthdr.len += m->m_len;
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if (!ISSET(rxcd->rxc_word0, VMXNET3_RXC_EOP))
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continue;
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/*
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* End of Packet
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*/
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if (letoh32(rxcd->rxc_word2 & VMXNET3_RXC_ERROR)) {
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ifp->if_ierrors++;
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m_freem(m);
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m_freem(comp_ring->sendmp);
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comp_ring->sendmp = comp_ring->lastmp = NULL;
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continue;
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}
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len = letoh32((rxcd->rxc_word2 >> VMXNET3_RXC_LEN_S) &
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VMXNET3_RXC_LEN_M);
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if (len < VMXNET3_MIN_MTU) {
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m_freem(m);
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if (comp_ring->sendmp->m_pkthdr.len < VMXNET3_MIN_MTU) {
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m_freem(comp_ring->sendmp);
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comp_ring->sendmp = comp_ring->lastmp = NULL;
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continue;
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}
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m->m_pkthdr.len = m->m_len = len;
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vmxnet3_rx_offload(rxcd, m);
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if (((letoh32(rxcd->rxc_word0) >> VMXNET3_RXC_RSSTYPE_S) &
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VMXNET3_RXC_RSSTYPE_M) != VMXNET3_RXC_RSSTYPE_NONE) {
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m->m_pkthdr.ph_flowid = letoh32(rxcd->rxc_word1);
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SET(m->m_pkthdr.csum_flags, M_FLOWID);
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comp_ring->sendmp->m_pkthdr.ph_flowid =
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letoh32(rxcd->rxc_word1);
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SET(comp_ring->sendmp->m_pkthdr.csum_flags, M_FLOWID);
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}
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ml_enqueue(&ml, m);
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vmxnet3_rx_offload(rxcd, comp_ring->sendmp);
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ml_enqueue(&ml, comp_ring->sendmp);
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comp_ring->sendmp = comp_ring->lastmp = NULL;
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}
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bus_dmamap_sync(sc->sc_dmat, VMX_DMA_MAP(&comp_ring->dmamem),
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@ -1144,19 +1196,20 @@ vmxnet3_rxintr(struct vmxnet3_softc *sc, struct vmxnet3_rxqueue *rq)
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comp_ring->next = next;
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comp_ring->gen = rgen;
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if (done == 0)
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return;
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for (int i = 0; i < 2; i++) {
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if (done[i] == 0)
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continue;
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ring = &rq->cmd_ring[0];
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ring = &rq->cmd_ring[i];
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if (ifiq_input(rq->ifiq, &ml))
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if_rxr_livelocked(&ring->rxr);
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if (ifiq_input(rq->ifiq, &ml))
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if_rxr_livelocked(&ring->rxr);
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/* XXX Should we (try to) allocate buffers for ring 2 too? */
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mtx_enter(&ring->mtx);
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if_rxr_put(&ring->rxr, done);
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vmxnet3_rxfill(ring);
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mtx_leave(&ring->mtx);
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mtx_enter(&ring->mtx);
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if_rxr_put(&ring->rxr, done[i]);
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vmxnet3_rxfill(ring);
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mtx_leave(&ring->mtx);
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}
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}
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void
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@ -1211,6 +1264,8 @@ vmxnet3_iff(struct vmxnet3_softc *sc)
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void
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vmxnet3_rx_offload(struct vmxnet3_rxcompdesc *rxcd, struct mbuf *m)
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{
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uint32_t pkts;
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/*
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* VLAN Offload
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*/
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@ -1243,6 +1298,45 @@ vmxnet3_rx_offload(struct vmxnet3_rxcompdesc *rxcd, struct mbuf *m)
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else if (ISSET(rxcd->rxc_word3, VMXNET3_RXC_UDP))
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SET(m->m_pkthdr.csum_flags, M_UDP_CSUM_IN_OK);
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}
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/*
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* TCP Large Receive Offload
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*/
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pkts = m->m_pkthdr.ph_mss;
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m->m_pkthdr.ph_mss = 0;
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if (pkts > 1) {
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struct ether_extracted ext;
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uint32_t paylen;
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ether_extract_headers(m, &ext);
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paylen = ext.iplen;
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if (ext.ip4 || ext.ip6)
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paylen -= ext.iphlen;
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if (ext.tcp) {
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paylen -= ext.tcphlen;
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tcpstat_inc(tcps_inhwlro);
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tcpstat_add(tcps_inpktlro, pkts);
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} else {
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tcpstat_inc(tcps_inbadlro);
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}
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/*
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* If we gonna forward this packet, we have to mark it as TSO,
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* set a correct mss, and recalculate the TCP checksum.
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*/
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if (ext.tcp && paylen >= pkts) {
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SET(m->m_pkthdr.csum_flags, M_TCP_TSO);
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m->m_pkthdr.ph_mss = paylen / pkts;
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}
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if (ext.tcp &&
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ISSET(m->m_pkthdr.csum_flags, M_TCP_CSUM_IN_OK)) {
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SET(m->m_pkthdr.csum_flags, M_TCP_CSUM_OUT);
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}
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}
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}
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void
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@ -1309,6 +1403,13 @@ vmxnet3_init(struct vmxnet3_softc *sc)
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return EIO;
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}
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/* TCP Large Receive Offload */
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if (ISSET(ifp->if_xflags, IFXF_LRO))
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SET(sc->sc_ds->upt_features, UPT1_F_LRO);
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else
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CLR(sc->sc_ds->upt_features, UPT1_F_LRO);
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WRITE_CMD(sc, VMXNET3_CMD_SET_FEATURE);
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/* Program promiscuous mode and multicast filters. */
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vmxnet3_iff(sc);
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@ -1,4 +1,4 @@
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/* $OpenBSD: if_vmxreg.h,v 1.9 2020/07/07 01:36:49 dlg Exp $ */
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/* $OpenBSD: if_vmxreg.h,v 1.10 2024/06/07 08:44:25 jan Exp $ */
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/*
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* Copyright (c) 2013 Tsubai Masanari
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@ -76,6 +76,7 @@ enum UPT1_RxStats {
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#define VMXNET3_CMD_RESET 0xcafe0002 /* reset device */
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#define VMXNET3_CMD_SET_RXMODE 0xcafe0003 /* set interface flags */
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#define VMXNET3_CMD_SET_FILTER 0xcafe0004 /* set address filter */
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#define VMXNET3_CMD_SET_FEATURE 0xcafe0009 /* set features */
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#define VMXNET3_CMD_GET_STATUS 0xf00d0000 /* get queue errors */
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#define VMXNET3_CMD_GET_STATS 0xf00d0001
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#define VMXNET3_CMD_GET_LINK 0xf00d0002 /* get link status */
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@ -189,6 +190,7 @@ struct vmxnet3_rxcompdesc {
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u_int32_t rxc_word1;
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#define VMXNET3_RXC_RSSHASH_M 0xffffffff /* RSS hash value */
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#define VMXNET3_RXC_RSSHASH_S 0
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#define VMXNET3_RXC_SEG_CNT_M 0x000000ff /* No. of seg. in LRO pkt */
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u_int32_t rxc_word2;
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#define VMXNET3_RXC_LEN_M 0x00003fff
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@ -210,6 +212,7 @@ struct vmxnet3_rxcompdesc {
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#define VMXNET3_RXC_FRAGMENT 0x00400000 /* IP fragment */
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#define VMXNET3_RXC_FCS 0x00800000 /* frame CRC correct */
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#define VMXNET3_RXC_TYPE_M 0x7f000000
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#define VMXNET3_RXC_TYPE_S 24
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#define VMXNET3_RXC_GEN_M 0x00000001U
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#define VMXNET3_RXC_GEN_S 31
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} __packed;
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@ -1,4 +1,4 @@
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/* $OpenBSD: igc_api.h,v 1.2 2022/05/11 06:14:15 kevlo Exp $ */
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/* $OpenBSD: igc_api.h,v 1.3 2024/06/09 05:18:12 jsg Exp $ */
|
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/*-
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* Copyright 2021 Intel Corp
|
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* Copyright 2021 Rubicon Communications, LLC (Netgate)
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|
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@ -20,35 +20,17 @@ int igc_setup_init_funcs(struct igc_hw *, bool);
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int igc_init_mac_params(struct igc_hw *);
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int igc_init_nvm_params(struct igc_hw *);
|
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int igc_init_phy_params(struct igc_hw *);
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int igc_get_bus_info(struct igc_hw *);
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void igc_clear_vfta(struct igc_hw *);
|
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void igc_write_vfta(struct igc_hw *, uint32_t, uint32_t);
|
||||
int igc_force_mac_fc(struct igc_hw *);
|
||||
int igc_check_for_link(struct igc_hw *);
|
||||
int igc_reset_hw(struct igc_hw *);
|
||||
int igc_init_hw(struct igc_hw *);
|
||||
int igc_setup_link(struct igc_hw *);
|
||||
int igc_get_speed_and_duplex(struct igc_hw *, uint16_t *,
|
||||
uint16_t *);
|
||||
int igc_disable_pcie_master(struct igc_hw *);
|
||||
void igc_config_collision_dist(struct igc_hw *);
|
||||
int igc_rar_set(struct igc_hw *, uint8_t *, uint32_t);
|
||||
uint32_t igc_hash_mc_addr(struct igc_hw *, uint8_t *);
|
||||
void igc_update_mc_addr_list(struct igc_hw *, uint8_t *, uint32_t);
|
||||
int igc_check_reset_block(struct igc_hw *);
|
||||
int igc_get_cable_length(struct igc_hw *);
|
||||
int igc_validate_mdi_setting(struct igc_hw *);
|
||||
int igc_get_phy_info(struct igc_hw *);
|
||||
int igc_phy_hw_reset(struct igc_hw *);
|
||||
void igc_power_up_phy(struct igc_hw *);
|
||||
void igc_power_down_phy(struct igc_hw *);
|
||||
int igc_read_mac_addr(struct igc_hw *);
|
||||
int igc_read_pba_string(struct igc_hw *, uint8_t *, uint32_t);
|
||||
void igc_reload_nvm(struct igc_hw *);
|
||||
int igc_validate_nvm_checksum(struct igc_hw *);
|
||||
int igc_read_nvm(struct igc_hw *, uint16_t, uint16_t, uint16_t *);
|
||||
int igc_write_nvm(struct igc_hw *, uint16_t, uint16_t, uint16_t *);
|
||||
int igc_set_d3_lplu_state(struct igc_hw *, bool);
|
||||
int igc_set_d0_lplu_state(struct igc_hw *, bool);
|
||||
|
||||
#endif /* _IGC_API_H_ */
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $OpenBSD: igc_mac.h,v 1.1 2021/10/31 14:52:57 patrick Exp $ */
|
||||
/* $OpenBSD: igc_mac.h,v 1.2 2024/06/09 05:18:12 jsg Exp $ */
|
||||
/*-
|
||||
* Copyright 2021 Intel Corp
|
||||
* Copyright 2021 Rubicon Communications, LLC (Netgate)
|
||||
|
|
@ -12,34 +12,23 @@
|
|||
|
||||
void igc_init_mac_ops_generic(struct igc_hw *);
|
||||
int igc_null_ops_generic(struct igc_hw *);
|
||||
int igc_null_link_info(struct igc_hw *, uint16_t *, uint16_t *);
|
||||
bool igc_null_mng_mode(struct igc_hw *);
|
||||
void igc_null_update_mc(struct igc_hw *, uint8_t *h, uint32_t);
|
||||
void igc_null_write_vfta(struct igc_hw *, uint32_t a, uint32_t);
|
||||
int igc_check_for_copper_link_generic(struct igc_hw *);
|
||||
int igc_config_fc_after_link_up_generic(struct igc_hw *);
|
||||
int igc_disable_pcie_master_generic(struct igc_hw *);
|
||||
int igc_force_mac_fc_generic(struct igc_hw *);
|
||||
int igc_get_auto_rd_done_generic(struct igc_hw *);
|
||||
int igc_get_bus_info_pcie_generic(struct igc_hw *);
|
||||
void igc_set_lan_id_single_port(struct igc_hw *);
|
||||
int igc_get_speed_and_duplex_copper_generic(struct igc_hw *, uint16_t *,
|
||||
uint16_t *);
|
||||
void igc_update_mc_addr_list_generic(struct igc_hw *, uint8_t *, uint32_t);
|
||||
int igc_rar_set_generic(struct igc_hw *, uint8_t *, uint32_t);
|
||||
int igc_set_fc_watermarks_generic(struct igc_hw *);
|
||||
int igc_setup_link_generic(struct igc_hw *);
|
||||
int igc_validate_mdi_setting_crossover_generic(struct igc_hw *);
|
||||
|
||||
int igc_hash_mc_addr_generic(struct igc_hw *, uint8_t *);
|
||||
|
||||
void igc_clear_hw_cntrs_base_generic(struct igc_hw *);
|
||||
void igc_clear_vfta_generic(struct igc_hw *);
|
||||
void igc_init_rx_addrs_generic(struct igc_hw *, uint16_t);
|
||||
void igc_pcix_mmrbc_workaround_generic(struct igc_hw *);
|
||||
void igc_put_hw_semaphore_generic(struct igc_hw *);
|
||||
int igc_check_alt_mac_addr_generic(struct igc_hw *);
|
||||
void igc_set_pcie_no_snoop_generic(struct igc_hw *, uint32_t);
|
||||
void igc_write_vfta_generic(struct igc_hw *, uint32_t, uint32_t);
|
||||
void igc_config_collision_dist_generic(struct igc_hw *);
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $OpenBSD: igc_nvm.h,v 1.1 2021/10/31 14:52:57 patrick Exp $ */
|
||||
/* $OpenBSD: igc_nvm.h,v 1.2 2024/06/09 05:18:12 jsg Exp $ */
|
||||
/*-
|
||||
* Copyright 2021 Intel Corp
|
||||
* Copyright 2021 Rubicon Communications, LLC (Netgate)
|
||||
|
|
@ -13,17 +13,11 @@
|
|||
void igc_init_nvm_ops_generic(struct igc_hw *);
|
||||
int igc_null_read_nvm(struct igc_hw *, uint16_t, uint16_t, uint16_t *);
|
||||
void igc_null_nvm_generic(struct igc_hw *);
|
||||
int igc_null_led_default(struct igc_hw *, uint16_t *);
|
||||
int igc_null_write_nvm(struct igc_hw *, uint16_t, uint16_t, uint16_t *);
|
||||
int igc_poll_eerd_eewr_done(struct igc_hw *, int);
|
||||
int igc_read_mac_addr_generic(struct igc_hw *);
|
||||
int igc_read_pba_string_generic(struct igc_hw *, uint8_t *, uint32_t);
|
||||
int igc_read_nvm_eerd(struct igc_hw *, uint16_t, uint16_t, uint16_t *);
|
||||
int igc_valid_led_default_generic(struct igc_hw *, uint16_t *);
|
||||
int igc_validate_nvm_checksum_generic(struct igc_hw *);
|
||||
int igc_write_nvm_spi(struct igc_hw *, uint16_t, uint16_t, uint16_t *);
|
||||
int igc_update_nvm_checksum_generic(struct igc_hw *);
|
||||
void igc_release_nvm_generic(struct igc_hw *);
|
||||
void igc_reload_nvm_generic(struct igc_hw *);
|
||||
|
||||
#endif /* _IGC_NVM_H_ */
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $OpenBSD: igc_phy.h,v 1.2 2022/05/11 06:14:15 kevlo Exp $ */
|
||||
/* $OpenBSD: igc_phy.h,v 1.3 2024/06/09 05:18:12 jsg Exp $ */
|
||||
/*-
|
||||
* Copyright 2021 Intel Corp
|
||||
* Copyright 2021 Rubicon Communications, LLC (Netgate)
|
||||
|
|
@ -20,13 +20,8 @@ int igc_check_downshift_generic(struct igc_hw *);
|
|||
int igc_check_reset_block_generic(struct igc_hw *);
|
||||
int igc_get_phy_id(struct igc_hw *);
|
||||
int igc_phy_hw_reset_generic(struct igc_hw *);
|
||||
int igc_phy_reset_dsp_generic(struct igc_hw *);
|
||||
int igc_set_d3_lplu_state_generic(struct igc_hw *, bool);
|
||||
int igc_setup_copper_link_generic(struct igc_hw *);
|
||||
int igc_phy_has_link_generic(struct igc_hw *, uint32_t, uint32_t, bool *);
|
||||
int igc_determine_phy_address(struct igc_hw *);
|
||||
int igc_enable_phy_wakeup_reg_access_bm(struct igc_hw *, uint16_t *);
|
||||
int igc_disable_phy_wakeup_reg_access_bm(struct igc_hw *, uint16_t *);
|
||||
void igc_power_up_phy_copper(struct igc_hw *);
|
||||
void igc_power_down_phy_copper(struct igc_hw *);
|
||||
int igc_read_phy_reg_mdic(struct igc_hw *, uint32_t offset, uint16_t *);
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $OpenBSD: ixgbe.h,v 1.35 2024/04/12 19:27:43 jan Exp $ */
|
||||
/* $OpenBSD: ixgbe.h,v 1.36 2024/06/09 05:18:12 jsg Exp $ */
|
||||
|
||||
/******************************************************************************
|
||||
|
||||
|
|
@ -268,10 +268,6 @@ int32_t ixgbe_init_hw(struct ixgbe_hw *hw);
|
|||
enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw);
|
||||
int32_t ixgbe_identify_phy(struct ixgbe_hw *hw);
|
||||
void ixgbe_flap_tx_laser(struct ixgbe_hw *hw);
|
||||
int32_t ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed,
|
||||
bool autoneg_wait_to_complete);
|
||||
int32_t ixgbe_setup_mac_link(struct ixgbe_hw *hw, ixgbe_link_speed speed,
|
||||
bool autoneg_wait_to_complete);
|
||||
int32_t ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
|
||||
bool *link_up, bool link_up_wait_to_complete);
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue