sync with OpenBSD -current
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parent
4544ef4a2e
commit
06882d626f
GPG key ID:
F42C07F07E2E35B7
49 changed files with 1832 additions and 835 deletions
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@ -395,7 +395,7 @@ static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned i
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struct evergreen_cs_track *track = p->track;
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struct eg_surface surf;
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unsigned pitch, slice, mslice;
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unsigned long offset;
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u64 offset;
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int r;
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mslice = G_028C6C_SLICE_MAX(track->cb_color_view[id]) + 1;
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@ -433,14 +433,14 @@ static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned i
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return r;
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}
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offset = track->cb_color_bo_offset[id] << 8;
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offset = (u64)track->cb_color_bo_offset[id] << 8;
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if (offset & (surf.base_align - 1)) {
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dev_warn(p->dev, "%s:%d cb[%d] bo base %ld not aligned with %ld\n",
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dev_warn(p->dev, "%s:%d cb[%d] bo base %llu not aligned with %ld\n",
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__func__, __LINE__, id, offset, surf.base_align);
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return -EINVAL;
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}
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offset += surf.layer_size * mslice;
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offset += (u64)surf.layer_size * mslice;
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if (offset > radeon_bo_size(track->cb_color_bo[id])) {
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/* old ddx are broken they allocate bo with w*h*bpp but
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* program slice with ALIGN(h, 8), catch this and patch
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@ -448,14 +448,14 @@ static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned i
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*/
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if (!surf.mode) {
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uint32_t *ib = p->ib.ptr;
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unsigned long tmp, nby, bsize, size, min = 0;
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u64 tmp, nby, bsize, size, min = 0;
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/* find the height the ddx wants */
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if (surf.nby > 8) {
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min = surf.nby - 8;
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}
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bsize = radeon_bo_size(track->cb_color_bo[id]);
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tmp = track->cb_color_bo_offset[id] << 8;
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tmp = (u64)track->cb_color_bo_offset[id] << 8;
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for (nby = surf.nby; nby > min; nby--) {
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size = nby * surf.nbx * surf.bpe * surf.nsamples;
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if ((tmp + size * mslice) <= bsize) {
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@ -467,7 +467,7 @@ static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned i
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slice = ((nby * surf.nbx) / 64) - 1;
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if (!evergreen_surface_check(p, &surf, "cb")) {
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/* check if this one works */
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tmp += surf.layer_size * mslice;
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tmp += (u64)surf.layer_size * mslice;
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if (tmp <= bsize) {
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ib[track->cb_color_slice_idx[id]] = slice;
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goto old_ddx_ok;
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@ -476,9 +476,9 @@ static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned i
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}
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}
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dev_warn(p->dev, "%s:%d cb[%d] bo too small (layer size %d, "
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"offset %d, max layer %d, bo size %ld, slice %d)\n",
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"offset %llu, max layer %d, bo size %ld, slice %d)\n",
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__func__, __LINE__, id, surf.layer_size,
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track->cb_color_bo_offset[id] << 8, mslice,
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(u64)track->cb_color_bo_offset[id] << 8, mslice,
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radeon_bo_size(track->cb_color_bo[id]), slice);
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dev_warn(p->dev, "%s:%d problematic surf: (%d %d) (%d %d %d %d %d %d %d)\n",
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__func__, __LINE__, surf.nbx, surf.nby,
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@ -562,7 +562,7 @@ static int evergreen_cs_track_validate_stencil(struct radeon_cs_parser *p)
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struct evergreen_cs_track *track = p->track;
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struct eg_surface surf;
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unsigned pitch, slice, mslice;
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unsigned long offset;
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u64 offset;
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int r;
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mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1;
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@ -608,18 +608,18 @@ static int evergreen_cs_track_validate_stencil(struct radeon_cs_parser *p)
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return r;
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}
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offset = track->db_s_read_offset << 8;
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offset = (u64)track->db_s_read_offset << 8;
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if (offset & (surf.base_align - 1)) {
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dev_warn(p->dev, "%s:%d stencil read bo base %ld not aligned with %ld\n",
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dev_warn(p->dev, "%s:%d stencil read bo base %llu not aligned with %ld\n",
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__func__, __LINE__, offset, surf.base_align);
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return -EINVAL;
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}
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offset += surf.layer_size * mslice;
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offset += (u64)surf.layer_size * mslice;
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if (offset > radeon_bo_size(track->db_s_read_bo)) {
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dev_warn(p->dev, "%s:%d stencil read bo too small (layer size %d, "
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"offset %ld, max layer %d, bo size %ld)\n",
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"offset %llu, max layer %d, bo size %ld)\n",
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__func__, __LINE__, surf.layer_size,
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(unsigned long)track->db_s_read_offset << 8, mslice,
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(u64)track->db_s_read_offset << 8, mslice,
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radeon_bo_size(track->db_s_read_bo));
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dev_warn(p->dev, "%s:%d stencil invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n",
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__func__, __LINE__, track->db_depth_size,
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@ -627,18 +627,18 @@ static int evergreen_cs_track_validate_stencil(struct radeon_cs_parser *p)
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return -EINVAL;
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}
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offset = track->db_s_write_offset << 8;
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offset = (u64)track->db_s_write_offset << 8;
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if (offset & (surf.base_align - 1)) {
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dev_warn(p->dev, "%s:%d stencil write bo base %ld not aligned with %ld\n",
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dev_warn(p->dev, "%s:%d stencil write bo base %llu not aligned with %ld\n",
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__func__, __LINE__, offset, surf.base_align);
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return -EINVAL;
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}
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offset += surf.layer_size * mslice;
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offset += (u64)surf.layer_size * mslice;
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if (offset > radeon_bo_size(track->db_s_write_bo)) {
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dev_warn(p->dev, "%s:%d stencil write bo too small (layer size %d, "
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"offset %ld, max layer %d, bo size %ld)\n",
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"offset %llu, max layer %d, bo size %ld)\n",
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__func__, __LINE__, surf.layer_size,
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(unsigned long)track->db_s_write_offset << 8, mslice,
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(u64)track->db_s_write_offset << 8, mslice,
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radeon_bo_size(track->db_s_write_bo));
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return -EINVAL;
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}
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@ -659,7 +659,7 @@ static int evergreen_cs_track_validate_depth(struct radeon_cs_parser *p)
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struct evergreen_cs_track *track = p->track;
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struct eg_surface surf;
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unsigned pitch, slice, mslice;
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unsigned long offset;
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u64 offset;
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int r;
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mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1;
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@ -706,34 +706,34 @@ static int evergreen_cs_track_validate_depth(struct radeon_cs_parser *p)
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return r;
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}
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offset = track->db_z_read_offset << 8;
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offset = (u64)track->db_z_read_offset << 8;
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if (offset & (surf.base_align - 1)) {
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dev_warn(p->dev, "%s:%d stencil read bo base %ld not aligned with %ld\n",
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dev_warn(p->dev, "%s:%d stencil read bo base %llu not aligned with %ld\n",
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__func__, __LINE__, offset, surf.base_align);
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return -EINVAL;
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}
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offset += surf.layer_size * mslice;
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offset += (u64)surf.layer_size * mslice;
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if (offset > radeon_bo_size(track->db_z_read_bo)) {
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dev_warn(p->dev, "%s:%d depth read bo too small (layer size %d, "
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"offset %ld, max layer %d, bo size %ld)\n",
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"offset %llu, max layer %d, bo size %ld)\n",
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__func__, __LINE__, surf.layer_size,
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(unsigned long)track->db_z_read_offset << 8, mslice,
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(u64)track->db_z_read_offset << 8, mslice,
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radeon_bo_size(track->db_z_read_bo));
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return -EINVAL;
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}
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offset = track->db_z_write_offset << 8;
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offset = (u64)track->db_z_write_offset << 8;
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if (offset & (surf.base_align - 1)) {
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dev_warn(p->dev, "%s:%d stencil write bo base %ld not aligned with %ld\n",
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dev_warn(p->dev, "%s:%d stencil write bo base %llu not aligned with %ld\n",
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__func__, __LINE__, offset, surf.base_align);
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return -EINVAL;
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}
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offset += surf.layer_size * mslice;
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offset += (u64)surf.layer_size * mslice;
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if (offset > radeon_bo_size(track->db_z_write_bo)) {
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dev_warn(p->dev, "%s:%d depth write bo too small (layer size %d, "
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"offset %ld, max layer %d, bo size %ld)\n",
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"offset %llu, max layer %d, bo size %ld)\n",
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__func__, __LINE__, surf.layer_size,
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(unsigned long)track->db_z_write_offset << 8, mslice,
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(u64)track->db_z_write_offset << 8, mslice,
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radeon_bo_size(track->db_z_write_bo));
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return -EINVAL;
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}
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