sync with OpenBSD -current
This commit is contained in:
parent
4544ef4a2e
commit
06882d626f
49 changed files with 1832 additions and 835 deletions
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@ -2065,26 +2065,29 @@ amdgpu_atombios_encoder_get_lcd_info(struct amdgpu_encoder *encoder)
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fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
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if (fake_edid_record->ucFakeEDIDLength) {
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struct edid *edid;
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int edid_size =
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max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
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edid = kmalloc(edid_size, GFP_KERNEL);
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if (edid) {
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memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
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fake_edid_record->ucFakeEDIDLength);
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int edid_size;
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if (fake_edid_record->ucFakeEDIDLength == 128)
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edid_size = fake_edid_record->ucFakeEDIDLength;
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else
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edid_size = fake_edid_record->ucFakeEDIDLength * 128;
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edid = kmemdup(&fake_edid_record->ucFakeEDIDString[0],
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edid_size, GFP_KERNEL);
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if (edid) {
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if (drm_edid_is_valid(edid)) {
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adev->mode_info.bios_hardcoded_edid = edid;
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adev->mode_info.bios_hardcoded_edid_size = edid_size;
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} else
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} else {
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kfree(edid);
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}
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}
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record += struct_size(fake_edid_record,
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ucFakeEDIDString,
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edid_size);
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} else {
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/* empty fake edid record must be 3 bytes long */
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record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD) + 1;
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}
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record += fake_edid_record->ucFakeEDIDLength ?
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struct_size(fake_edid_record,
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ucFakeEDIDString,
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fake_edid_record->ucFakeEDIDLength) :
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/* empty fake edid record must be 3 bytes long */
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sizeof(ATOM_FAKE_EDID_PATCH_RECORD) + 1;
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break;
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case LCD_PANEL_RESOLUTION_RECORD_TYPE:
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panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
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@ -209,7 +209,7 @@ struct amd_sriov_msg_pf2vf_info {
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uint32_t pcie_atomic_ops_support_flags;
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/* reserved */
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uint32_t reserved[256 - AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE];
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};
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} __packed;
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struct amd_sriov_msg_vf2pf_info_header {
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/* the total structure size in byte */
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@ -267,7 +267,7 @@ struct amd_sriov_msg_vf2pf_info {
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/* reserved */
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uint32_t reserved[256 - AMD_SRIOV_MSG_VF2PF_INFO_FILLED_SIZE];
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};
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} __packed;
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/* mailbox message send from guest to host */
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enum amd_sriov_mailbox_request_message {
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@ -4041,6 +4041,7 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
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#define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
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#define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
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#define AMDGPU_DM_MIN_SPREAD ((AMDGPU_DM_DEFAULT_MAX_BACKLIGHT - AMDGPU_DM_DEFAULT_MIN_BACKLIGHT) / 2)
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#define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
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static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
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@ -4055,6 +4056,21 @@ static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
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return;
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amdgpu_acpi_get_backlight_caps(&caps);
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/* validate the firmware value is sane */
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if (caps.caps_valid) {
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int spread = caps.max_input_signal - caps.min_input_signal;
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if (caps.max_input_signal > AMDGPU_DM_DEFAULT_MAX_BACKLIGHT ||
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caps.min_input_signal < AMDGPU_DM_DEFAULT_MIN_BACKLIGHT ||
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spread > AMDGPU_DM_DEFAULT_MAX_BACKLIGHT ||
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spread < AMDGPU_DM_MIN_SPREAD) {
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DRM_DEBUG_KMS("DM: Invalid backlight caps: min=%d, max=%d\n",
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caps.min_input_signal, caps.max_input_signal);
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caps.caps_valid = false;
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}
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}
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if (caps.caps_valid) {
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dm->backlight_caps[bl_idx].caps_valid = true;
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if (caps.aux_support)
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@ -246,7 +246,7 @@ static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnecto
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aconnector->dsc_aux = &aconnector->mst_root->dm_dp_aux.aux;
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/* synaptics cascaded MST hub case */
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if (!aconnector->dsc_aux && is_synaptics_cascaded_panamera(aconnector->dc_link, port))
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if (is_synaptics_cascaded_panamera(aconnector->dc_link, port))
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aconnector->dsc_aux = port->mgr->aux;
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if (!aconnector->dsc_aux)
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@ -1115,7 +1115,7 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
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params[count].num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
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params[count].bpp_overwrite = aconnector->dsc_settings.dsc_bits_per_pixel;
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params[count].compression_possible = stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported;
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dc_dsc_get_policy_for_timing(params[count].timing, 0, &dsc_policy);
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dc_dsc_get_policy_for_timing(params[count].timing, 0, &dsc_policy, dc_link_get_highest_encoding_format(stream->link));
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if (!dc_dsc_compute_bandwidth_range(
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stream->sink->ctx->dc->res_pool->dscs[0],
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stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
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@ -1583,7 +1583,7 @@ static bool is_dsc_common_config_possible(struct dc_stream_state *stream,
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{
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struct dc_dsc_policy dsc_policy = {0};
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dc_dsc_get_policy_for_timing(&stream->timing, 0, &dsc_policy);
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dc_dsc_get_policy_for_timing(&stream->timing, 0, &dsc_policy, dc_link_get_highest_encoding_format(stream->link));
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dc_dsc_compute_bandwidth_range(stream->sink->ctx->dc->res_pool->dscs[0],
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stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
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dsc_policy.min_target_bpp * 16,
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@ -100,7 +100,8 @@ uint32_t dc_dsc_stream_bandwidth_overhead_in_kbps(
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*/
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void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing,
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uint32_t max_target_bpp_limit_override_x16,
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struct dc_dsc_policy *policy);
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struct dc_dsc_policy *policy,
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const enum dc_link_encoding_format link_encoding);
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void dc_dsc_policy_set_max_target_bpp_limit(uint32_t limit);
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@ -214,7 +214,11 @@ bool dcn30_set_output_transfer_func(struct dc *dc,
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}
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}
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mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
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if (mpc->funcs->set_output_gamma)
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mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
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else
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DC_LOG_ERROR("%s: set_output_gamma function pointer is NULL.\n", __func__);
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return ret;
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}
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@ -861,7 +861,7 @@ static bool setup_dsc_config(
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memset(dsc_cfg, 0, sizeof(struct dc_dsc_config));
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dc_dsc_get_policy_for_timing(timing, options->max_target_bpp_limit_override_x16, &policy);
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dc_dsc_get_policy_for_timing(timing, options->max_target_bpp_limit_override_x16, &policy, link_encoding);
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pic_width = timing->h_addressable + timing->h_border_left + timing->h_border_right;
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pic_height = timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
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@ -1134,7 +1134,8 @@ uint32_t dc_dsc_stream_bandwidth_overhead_in_kbps(
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void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing,
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uint32_t max_target_bpp_limit_override_x16,
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struct dc_dsc_policy *policy)
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struct dc_dsc_policy *policy,
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const enum dc_link_encoding_format link_encoding)
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{
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uint32_t bpc = 0;
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@ -133,7 +133,7 @@ unsigned int mod_freesync_calc_v_total_from_refresh(
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v_total = div64_u64(div64_u64(((unsigned long long)(
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frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)),
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stream->timing.h_total), 1000000);
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stream->timing.h_total) + 500000, 1000000);
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/* v_total cannot be less than nominal */
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if (v_total < stream->timing.v_total) {
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@ -395,7 +395,7 @@ static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned i
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struct evergreen_cs_track *track = p->track;
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struct eg_surface surf;
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unsigned pitch, slice, mslice;
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unsigned long offset;
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u64 offset;
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int r;
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mslice = G_028C6C_SLICE_MAX(track->cb_color_view[id]) + 1;
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@ -433,14 +433,14 @@ static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned i
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return r;
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}
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offset = track->cb_color_bo_offset[id] << 8;
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offset = (u64)track->cb_color_bo_offset[id] << 8;
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if (offset & (surf.base_align - 1)) {
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dev_warn(p->dev, "%s:%d cb[%d] bo base %ld not aligned with %ld\n",
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dev_warn(p->dev, "%s:%d cb[%d] bo base %llu not aligned with %ld\n",
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__func__, __LINE__, id, offset, surf.base_align);
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return -EINVAL;
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}
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offset += surf.layer_size * mslice;
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offset += (u64)surf.layer_size * mslice;
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if (offset > radeon_bo_size(track->cb_color_bo[id])) {
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/* old ddx are broken they allocate bo with w*h*bpp but
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* program slice with ALIGN(h, 8), catch this and patch
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*/
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if (!surf.mode) {
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uint32_t *ib = p->ib.ptr;
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unsigned long tmp, nby, bsize, size, min = 0;
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u64 tmp, nby, bsize, size, min = 0;
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/* find the height the ddx wants */
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if (surf.nby > 8) {
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min = surf.nby - 8;
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}
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bsize = radeon_bo_size(track->cb_color_bo[id]);
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tmp = track->cb_color_bo_offset[id] << 8;
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tmp = (u64)track->cb_color_bo_offset[id] << 8;
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for (nby = surf.nby; nby > min; nby--) {
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size = nby * surf.nbx * surf.bpe * surf.nsamples;
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if ((tmp + size * mslice) <= bsize) {
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slice = ((nby * surf.nbx) / 64) - 1;
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if (!evergreen_surface_check(p, &surf, "cb")) {
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/* check if this one works */
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tmp += surf.layer_size * mslice;
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tmp += (u64)surf.layer_size * mslice;
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if (tmp <= bsize) {
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ib[track->cb_color_slice_idx[id]] = slice;
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goto old_ddx_ok;
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@ -476,9 +476,9 @@ static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned i
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}
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}
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dev_warn(p->dev, "%s:%d cb[%d] bo too small (layer size %d, "
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"offset %d, max layer %d, bo size %ld, slice %d)\n",
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"offset %llu, max layer %d, bo size %ld, slice %d)\n",
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__func__, __LINE__, id, surf.layer_size,
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track->cb_color_bo_offset[id] << 8, mslice,
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(u64)track->cb_color_bo_offset[id] << 8, mslice,
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radeon_bo_size(track->cb_color_bo[id]), slice);
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dev_warn(p->dev, "%s:%d problematic surf: (%d %d) (%d %d %d %d %d %d %d)\n",
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__func__, __LINE__, surf.nbx, surf.nby,
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@ -562,7 +562,7 @@ static int evergreen_cs_track_validate_stencil(struct radeon_cs_parser *p)
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struct evergreen_cs_track *track = p->track;
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struct eg_surface surf;
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unsigned pitch, slice, mslice;
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unsigned long offset;
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u64 offset;
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int r;
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mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1;
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@ -608,18 +608,18 @@ static int evergreen_cs_track_validate_stencil(struct radeon_cs_parser *p)
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return r;
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}
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offset = track->db_s_read_offset << 8;
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offset = (u64)track->db_s_read_offset << 8;
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if (offset & (surf.base_align - 1)) {
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dev_warn(p->dev, "%s:%d stencil read bo base %ld not aligned with %ld\n",
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dev_warn(p->dev, "%s:%d stencil read bo base %llu not aligned with %ld\n",
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__func__, __LINE__, offset, surf.base_align);
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return -EINVAL;
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}
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offset += surf.layer_size * mslice;
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offset += (u64)surf.layer_size * mslice;
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if (offset > radeon_bo_size(track->db_s_read_bo)) {
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dev_warn(p->dev, "%s:%d stencil read bo too small (layer size %d, "
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"offset %ld, max layer %d, bo size %ld)\n",
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"offset %llu, max layer %d, bo size %ld)\n",
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__func__, __LINE__, surf.layer_size,
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(unsigned long)track->db_s_read_offset << 8, mslice,
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(u64)track->db_s_read_offset << 8, mslice,
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radeon_bo_size(track->db_s_read_bo));
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dev_warn(p->dev, "%s:%d stencil invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n",
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__func__, __LINE__, track->db_depth_size,
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@ -627,18 +627,18 @@ static int evergreen_cs_track_validate_stencil(struct radeon_cs_parser *p)
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return -EINVAL;
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}
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offset = track->db_s_write_offset << 8;
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offset = (u64)track->db_s_write_offset << 8;
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if (offset & (surf.base_align - 1)) {
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dev_warn(p->dev, "%s:%d stencil write bo base %ld not aligned with %ld\n",
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dev_warn(p->dev, "%s:%d stencil write bo base %llu not aligned with %ld\n",
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__func__, __LINE__, offset, surf.base_align);
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return -EINVAL;
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}
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offset += surf.layer_size * mslice;
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offset += (u64)surf.layer_size * mslice;
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if (offset > radeon_bo_size(track->db_s_write_bo)) {
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dev_warn(p->dev, "%s:%d stencil write bo too small (layer size %d, "
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"offset %ld, max layer %d, bo size %ld)\n",
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"offset %llu, max layer %d, bo size %ld)\n",
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__func__, __LINE__, surf.layer_size,
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(unsigned long)track->db_s_write_offset << 8, mslice,
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(u64)track->db_s_write_offset << 8, mslice,
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radeon_bo_size(track->db_s_write_bo));
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return -EINVAL;
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}
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@ -659,7 +659,7 @@ static int evergreen_cs_track_validate_depth(struct radeon_cs_parser *p)
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struct evergreen_cs_track *track = p->track;
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struct eg_surface surf;
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unsigned pitch, slice, mslice;
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unsigned long offset;
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u64 offset;
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int r;
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mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1;
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@ -706,34 +706,34 @@ static int evergreen_cs_track_validate_depth(struct radeon_cs_parser *p)
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return r;
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}
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offset = track->db_z_read_offset << 8;
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offset = (u64)track->db_z_read_offset << 8;
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if (offset & (surf.base_align - 1)) {
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dev_warn(p->dev, "%s:%d stencil read bo base %ld not aligned with %ld\n",
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dev_warn(p->dev, "%s:%d stencil read bo base %llu not aligned with %ld\n",
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__func__, __LINE__, offset, surf.base_align);
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return -EINVAL;
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}
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offset += surf.layer_size * mslice;
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offset += (u64)surf.layer_size * mslice;
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if (offset > radeon_bo_size(track->db_z_read_bo)) {
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dev_warn(p->dev, "%s:%d depth read bo too small (layer size %d, "
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"offset %ld, max layer %d, bo size %ld)\n",
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"offset %llu, max layer %d, bo size %ld)\n",
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__func__, __LINE__, surf.layer_size,
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(unsigned long)track->db_z_read_offset << 8, mslice,
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(u64)track->db_z_read_offset << 8, mslice,
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radeon_bo_size(track->db_z_read_bo));
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return -EINVAL;
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}
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offset = track->db_z_write_offset << 8;
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offset = (u64)track->db_z_write_offset << 8;
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if (offset & (surf.base_align - 1)) {
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dev_warn(p->dev, "%s:%d stencil write bo base %ld not aligned with %ld\n",
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dev_warn(p->dev, "%s:%d stencil write bo base %llu not aligned with %ld\n",
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__func__, __LINE__, offset, surf.base_align);
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return -EINVAL;
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}
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offset += surf.layer_size * mslice;
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offset += (u64)surf.layer_size * mslice;
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if (offset > radeon_bo_size(track->db_z_write_bo)) {
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dev_warn(p->dev, "%s:%d depth write bo too small (layer size %d, "
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"offset %ld, max layer %d, bo size %ld)\n",
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"offset %llu, max layer %d, bo size %ld)\n",
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__func__, __LINE__, surf.layer_size,
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(unsigned long)track->db_z_write_offset << 8, mslice,
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(u64)track->db_z_write_offset << 8, mslice,
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radeon_bo_size(track->db_z_write_bo));
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return -EINVAL;
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}
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@ -1720,26 +1720,29 @@ struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
|
|||
fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
|
||||
if (fake_edid_record->ucFakeEDIDLength) {
|
||||
struct edid *edid;
|
||||
int edid_size =
|
||||
max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
|
||||
edid = kmalloc(edid_size, GFP_KERNEL);
|
||||
if (edid) {
|
||||
memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
|
||||
fake_edid_record->ucFakeEDIDLength);
|
||||
int edid_size;
|
||||
|
||||
if (fake_edid_record->ucFakeEDIDLength == 128)
|
||||
edid_size = fake_edid_record->ucFakeEDIDLength;
|
||||
else
|
||||
edid_size = fake_edid_record->ucFakeEDIDLength * 128;
|
||||
edid = kmemdup(&fake_edid_record->ucFakeEDIDString[0],
|
||||
edid_size, GFP_KERNEL);
|
||||
if (edid) {
|
||||
if (drm_edid_is_valid(edid)) {
|
||||
rdev->mode_info.bios_hardcoded_edid = edid;
|
||||
rdev->mode_info.bios_hardcoded_edid_size = edid_size;
|
||||
} else
|
||||
} else {
|
||||
kfree(edid);
|
||||
}
|
||||
}
|
||||
record += struct_size(fake_edid_record,
|
||||
ucFakeEDIDString,
|
||||
edid_size);
|
||||
} else {
|
||||
/* empty fake edid record must be 3 bytes long */
|
||||
record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD) + 1;
|
||||
}
|
||||
record += fake_edid_record->ucFakeEDIDLength ?
|
||||
struct_size(fake_edid_record,
|
||||
ucFakeEDIDString,
|
||||
fake_edid_record->ucFakeEDIDLength) :
|
||||
/* empty fake edid record must be 3 bytes long */
|
||||
sizeof(ATOM_FAKE_EDID_PATCH_RECORD) + 1;
|
||||
break;
|
||||
case LCD_PANEL_RESOLUTION_RECORD_TYPE:
|
||||
panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue