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sync with OpenBSD -current

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This commit is contained in:
purplerain 2024-10-07 23:11:56 +00:00
parent 4544ef4a2e
commit 06882d626f
Signed by: purplerain
GPG key ID: F42C07F07E2E35B7
49 changed files with 1832 additions and 835 deletions
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29
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios_encoders.c
View file

@ -2065,26 +2065,29 @@ amdgpu_atombios_encoder_get_lcd_info(struct amdgpu_encoder *encoder)
fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
if (fake_edid_record->ucFakeEDIDLength) {
struct edid *edid;
int edid_size =
max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
edid = kmalloc(edid_size, GFP_KERNEL);
if (edid) {
memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
fake_edid_record->ucFakeEDIDLength);
int edid_size;
if (fake_edid_record->ucFakeEDIDLength == 128)
edid_size = fake_edid_record->ucFakeEDIDLength;
else
edid_size = fake_edid_record->ucFakeEDIDLength * 128;
edid = kmemdup(&fake_edid_record->ucFakeEDIDString[0],
edid_size, GFP_KERNEL);
if (edid) {
if (drm_edid_is_valid(edid)) {
adev->mode_info.bios_hardcoded_edid = edid;
adev->mode_info.bios_hardcoded_edid_size = edid_size;
} else
} else {
kfree(edid);
}
}
record += struct_size(fake_edid_record,
ucFakeEDIDString,
edid_size);
} else {
/* empty fake edid record must be 3 bytes long */
record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD) + 1;
}
record += fake_edid_record->ucFakeEDIDLength ?
struct_size(fake_edid_record,
ucFakeEDIDString,
fake_edid_record->ucFakeEDIDLength) :
/* empty fake edid record must be 3 bytes long */
sizeof(ATOM_FAKE_EDID_PATCH_RECORD) + 1;
break;
case LCD_PANEL_RESOLUTION_RECORD_TYPE:
panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;

4
sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h
View file

@ -209,7 +209,7 @@ struct amd_sriov_msg_pf2vf_info {
uint32_t pcie_atomic_ops_support_flags;
/* reserved */
uint32_t reserved[256 - AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE];
};
} __packed;
struct amd_sriov_msg_vf2pf_info_header {
/* the total structure size in byte */
@ -267,7 +267,7 @@ struct amd_sriov_msg_vf2pf_info {
/* reserved */
uint32_t reserved[256 - AMD_SRIOV_MSG_VF2PF_INFO_FILLED_SIZE];
};
} __packed;
/* mailbox message send from guest to host */
enum amd_sriov_mailbox_request_message {

16
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
View file

@ -4041,6 +4041,7 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
#define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
#define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
#define AMDGPU_DM_MIN_SPREAD ((AMDGPU_DM_DEFAULT_MAX_BACKLIGHT - AMDGPU_DM_DEFAULT_MIN_BACKLIGHT) / 2)
#define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
@ -4055,6 +4056,21 @@ static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
return;
amdgpu_acpi_get_backlight_caps(&caps);
/* validate the firmware value is sane */
if (caps.caps_valid) {
int spread = caps.max_input_signal - caps.min_input_signal;
if (caps.max_input_signal > AMDGPU_DM_DEFAULT_MAX_BACKLIGHT ||
caps.min_input_signal < AMDGPU_DM_DEFAULT_MIN_BACKLIGHT ||
spread > AMDGPU_DM_DEFAULT_MAX_BACKLIGHT ||
spread < AMDGPU_DM_MIN_SPREAD) {
DRM_DEBUG_KMS("DM: Invalid backlight caps: min=%d, max=%d\n",
caps.min_input_signal, caps.max_input_signal);
caps.caps_valid = false;
}
}
if (caps.caps_valid) {
dm->backlight_caps[bl_idx].caps_valid = true;
if (caps.aux_support)

6
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
View file

@ -246,7 +246,7 @@ static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnecto
aconnector->dsc_aux = &aconnector->mst_root->dm_dp_aux.aux;
/* synaptics cascaded MST hub case */
if (!aconnector->dsc_aux && is_synaptics_cascaded_panamera(aconnector->dc_link, port))
if (is_synaptics_cascaded_panamera(aconnector->dc_link, port))
aconnector->dsc_aux = port->mgr->aux;
if (!aconnector->dsc_aux)
@ -1115,7 +1115,7 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
params[count].num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
params[count].bpp_overwrite = aconnector->dsc_settings.dsc_bits_per_pixel;
params[count].compression_possible = stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported;
dc_dsc_get_policy_for_timing(params[count].timing, 0, &dsc_policy);
dc_dsc_get_policy_for_timing(params[count].timing, 0, &dsc_policy, dc_link_get_highest_encoding_format(stream->link));
if (!dc_dsc_compute_bandwidth_range(
stream->sink->ctx->dc->res_pool->dscs[0],
stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
@ -1583,7 +1583,7 @@ static bool is_dsc_common_config_possible(struct dc_stream_state *stream,
{
struct dc_dsc_policy dsc_policy = {0};
dc_dsc_get_policy_for_timing(&stream->timing, 0, &dsc_policy);
dc_dsc_get_policy_for_timing(&stream->timing, 0, &dsc_policy, dc_link_get_highest_encoding_format(stream->link));
dc_dsc_compute_bandwidth_range(stream->sink->ctx->dc->res_pool->dscs[0],
stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
dsc_policy.min_target_bpp * 16,

3
sys/dev/pci/drm/amd/display/dc/dc_dsc.h
View file

@ -100,7 +100,8 @@ uint32_t dc_dsc_stream_bandwidth_overhead_in_kbps(
*/
void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing,
uint32_t max_target_bpp_limit_override_x16,
struct dc_dsc_policy *policy);
struct dc_dsc_policy *policy,
const enum dc_link_encoding_format link_encoding);
void dc_dsc_policy_set_max_target_bpp_limit(uint32_t limit);

6
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_hwseq.c
View file

@ -214,7 +214,11 @@ bool dcn30_set_output_transfer_func(struct dc *dc,
}
}
mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
if (mpc->funcs->set_output_gamma)
mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
else
DC_LOG_ERROR("%s: set_output_gamma function pointer is NULL.\n", __func__);
return ret;
}

5
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
View file

@ -861,7 +861,7 @@ static bool setup_dsc_config(
memset(dsc_cfg, 0, sizeof(struct dc_dsc_config));
dc_dsc_get_policy_for_timing(timing, options->max_target_bpp_limit_override_x16, &policy);
dc_dsc_get_policy_for_timing(timing, options->max_target_bpp_limit_override_x16, &policy, link_encoding);
pic_width = timing->h_addressable + timing->h_border_left + timing->h_border_right;
pic_height = timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
@ -1134,7 +1134,8 @@ uint32_t dc_dsc_stream_bandwidth_overhead_in_kbps(
void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing,
uint32_t max_target_bpp_limit_override_x16,
struct dc_dsc_policy *policy)
struct dc_dsc_policy *policy,
const enum dc_link_encoding_format link_encoding)
{
uint32_t bpc = 0;

2
sys/dev/pci/drm/amd/display/modules/freesync/freesync.c
View file

@ -133,7 +133,7 @@ unsigned int mod_freesync_calc_v_total_from_refresh(
v_total = div64_u64(div64_u64(((unsigned long long)(
frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)),
stream->timing.h_total), 1000000);
stream->timing.h_total) + 500000, 1000000);
/* v_total cannot be less than nominal */
if (v_total < stream->timing.v_total) {

62
sys/dev/pci/drm/radeon/evergreen_cs.c
View file

@ -395,7 +395,7 @@ static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned i
struct evergreen_cs_track *track = p->track;
struct eg_surface surf;
unsigned pitch, slice, mslice;
unsigned long offset;
u64 offset;
int r;
mslice = G_028C6C_SLICE_MAX(track->cb_color_view[id]) + 1;
@ -433,14 +433,14 @@ static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned i
return r;
}
offset = track->cb_color_bo_offset[id] << 8;
offset = (u64)track->cb_color_bo_offset[id] << 8;
if (offset & (surf.base_align - 1)) {
dev_warn(p->dev, "%s:%d cb[%d] bo base %ld not aligned with %ld\n",
dev_warn(p->dev, "%s:%d cb[%d] bo base %llu not aligned with %ld\n",
__func__, __LINE__, id, offset, surf.base_align);
return -EINVAL;
}
offset += surf.layer_size * mslice;
offset += (u64)surf.layer_size * mslice;
if (offset > radeon_bo_size(track->cb_color_bo[id])) {
/* old ddx are broken they allocate bo with w*h*bpp but
* program slice with ALIGN(h, 8), catch this and patch
@ -448,14 +448,14 @@ static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned i
*/
if (!surf.mode) {
uint32_t *ib = p->ib.ptr;
unsigned long tmp, nby, bsize, size, min = 0;
u64 tmp, nby, bsize, size, min = 0;
/* find the height the ddx wants */
if (surf.nby > 8) {
min = surf.nby - 8;
}
bsize = radeon_bo_size(track->cb_color_bo[id]);
tmp = track->cb_color_bo_offset[id] << 8;
tmp = (u64)track->cb_color_bo_offset[id] << 8;
for (nby = surf.nby; nby > min; nby--) {
size = nby * surf.nbx * surf.bpe * surf.nsamples;
if ((tmp + size * mslice) <= bsize) {
@ -467,7 +467,7 @@ static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned i
slice = ((nby * surf.nbx) / 64) - 1;
if (!evergreen_surface_check(p, &surf, "cb")) {
/* check if this one works */
tmp += surf.layer_size * mslice;
tmp += (u64)surf.layer_size * mslice;
if (tmp <= bsize) {
ib[track->cb_color_slice_idx[id]] = slice;
goto old_ddx_ok;
@ -476,9 +476,9 @@ static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned i
}
}
dev_warn(p->dev, "%s:%d cb[%d] bo too small (layer size %d, "
"offset %d, max layer %d, bo size %ld, slice %d)\n",
"offset %llu, max layer %d, bo size %ld, slice %d)\n",
__func__, __LINE__, id, surf.layer_size,
track->cb_color_bo_offset[id] << 8, mslice,
(u64)track->cb_color_bo_offset[id] << 8, mslice,
radeon_bo_size(track->cb_color_bo[id]), slice);
dev_warn(p->dev, "%s:%d problematic surf: (%d %d) (%d %d %d %d %d %d %d)\n",
__func__, __LINE__, surf.nbx, surf.nby,
@ -562,7 +562,7 @@ static int evergreen_cs_track_validate_stencil(struct radeon_cs_parser *p)
struct evergreen_cs_track *track = p->track;
struct eg_surface surf;
unsigned pitch, slice, mslice;
unsigned long offset;
u64 offset;
int r;
mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1;
@ -608,18 +608,18 @@ static int evergreen_cs_track_validate_stencil(struct radeon_cs_parser *p)
return r;
}
offset = track->db_s_read_offset << 8;
offset = (u64)track->db_s_read_offset << 8;
if (offset & (surf.base_align - 1)) {
dev_warn(p->dev, "%s:%d stencil read bo base %ld not aligned with %ld\n",
dev_warn(p->dev, "%s:%d stencil read bo base %llu not aligned with %ld\n",
__func__, __LINE__, offset, surf.base_align);
return -EINVAL;
}
offset += surf.layer_size * mslice;
offset += (u64)surf.layer_size * mslice;
if (offset > radeon_bo_size(track->db_s_read_bo)) {
dev_warn(p->dev, "%s:%d stencil read bo too small (layer size %d, "
"offset %ld, max layer %d, bo size %ld)\n",
"offset %llu, max layer %d, bo size %ld)\n",
__func__, __LINE__, surf.layer_size,
(unsigned long)track->db_s_read_offset << 8, mslice,
(u64)track->db_s_read_offset << 8, mslice,
radeon_bo_size(track->db_s_read_bo));
dev_warn(p->dev, "%s:%d stencil invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n",
__func__, __LINE__, track->db_depth_size,
@ -627,18 +627,18 @@ static int evergreen_cs_track_validate_stencil(struct radeon_cs_parser *p)
return -EINVAL;
}
offset = track->db_s_write_offset << 8;
offset = (u64)track->db_s_write_offset << 8;
if (offset & (surf.base_align - 1)) {
dev_warn(p->dev, "%s:%d stencil write bo base %ld not aligned with %ld\n",
dev_warn(p->dev, "%s:%d stencil write bo base %llu not aligned with %ld\n",
__func__, __LINE__, offset, surf.base_align);
return -EINVAL;
}
offset += surf.layer_size * mslice;
offset += (u64)surf.layer_size * mslice;
if (offset > radeon_bo_size(track->db_s_write_bo)) {
dev_warn(p->dev, "%s:%d stencil write bo too small (layer size %d, "
"offset %ld, max layer %d, bo size %ld)\n",
"offset %llu, max layer %d, bo size %ld)\n",
__func__, __LINE__, surf.layer_size,
(unsigned long)track->db_s_write_offset << 8, mslice,
(u64)track->db_s_write_offset << 8, mslice,
radeon_bo_size(track->db_s_write_bo));
return -EINVAL;
}
@ -659,7 +659,7 @@ static int evergreen_cs_track_validate_depth(struct radeon_cs_parser *p)
struct evergreen_cs_track *track = p->track;
struct eg_surface surf;
unsigned pitch, slice, mslice;
unsigned long offset;
u64 offset;
int r;
mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1;
@ -706,34 +706,34 @@ static int evergreen_cs_track_validate_depth(struct radeon_cs_parser *p)
return r;
}
offset = track->db_z_read_offset << 8;
offset = (u64)track->db_z_read_offset << 8;
if (offset & (surf.base_align - 1)) {
dev_warn(p->dev, "%s:%d stencil read bo base %ld not aligned with %ld\n",
dev_warn(p->dev, "%s:%d stencil read bo base %llu not aligned with %ld\n",
__func__, __LINE__, offset, surf.base_align);
return -EINVAL;
}
offset += surf.layer_size * mslice;
offset += (u64)surf.layer_size * mslice;
if (offset > radeon_bo_size(track->db_z_read_bo)) {
dev_warn(p->dev, "%s:%d depth read bo too small (layer size %d, "
"offset %ld, max layer %d, bo size %ld)\n",
"offset %llu, max layer %d, bo size %ld)\n",
__func__, __LINE__, surf.layer_size,
(unsigned long)track->db_z_read_offset << 8, mslice,
(u64)track->db_z_read_offset << 8, mslice,
radeon_bo_size(track->db_z_read_bo));
return -EINVAL;
}
offset = track->db_z_write_offset << 8;
offset = (u64)track->db_z_write_offset << 8;
if (offset & (surf.base_align - 1)) {
dev_warn(p->dev, "%s:%d stencil write bo base %ld not aligned with %ld\n",
dev_warn(p->dev, "%s:%d stencil write bo base %llu not aligned with %ld\n",
__func__, __LINE__, offset, surf.base_align);
return -EINVAL;
}
offset += surf.layer_size * mslice;
offset += (u64)surf.layer_size * mslice;
if (offset > radeon_bo_size(track->db_z_write_bo)) {
dev_warn(p->dev, "%s:%d depth write bo too small (layer size %d, "
"offset %ld, max layer %d, bo size %ld)\n",
"offset %llu, max layer %d, bo size %ld)\n",
__func__, __LINE__, surf.layer_size,
(unsigned long)track->db_z_write_offset << 8, mslice,
(u64)track->db_z_write_offset << 8, mslice,
radeon_bo_size(track->db_z_write_bo));
return -EINVAL;
}

29
sys/dev/pci/drm/radeon/radeon_atombios.c
View file

@ -1720,26 +1720,29 @@ struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
if (fake_edid_record->ucFakeEDIDLength) {
struct edid *edid;
int edid_size =
max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
edid = kmalloc(edid_size, GFP_KERNEL);
if (edid) {
memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
fake_edid_record->ucFakeEDIDLength);
int edid_size;
if (fake_edid_record->ucFakeEDIDLength == 128)
edid_size = fake_edid_record->ucFakeEDIDLength;
else
edid_size = fake_edid_record->ucFakeEDIDLength * 128;
edid = kmemdup(&fake_edid_record->ucFakeEDIDString[0],
edid_size, GFP_KERNEL);
if (edid) {
if (drm_edid_is_valid(edid)) {
rdev->mode_info.bios_hardcoded_edid = edid;
rdev->mode_info.bios_hardcoded_edid_size = edid_size;
} else
} else {
kfree(edid);
}
}
record += struct_size(fake_edid_record,
ucFakeEDIDString,
edid_size);
} else {
/* empty fake edid record must be 3 bytes long */
record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD) + 1;
}
record += fake_edid_record->ucFakeEDIDLength ?
struct_size(fake_edid_record,
ucFakeEDIDString,
fake_edid_record->ucFakeEDIDLength) :
/* empty fake edid record must be 3 bytes long */
sizeof(ATOM_FAKE_EDID_PATCH_RECORD) + 1;
break;
case LCD_PANEL_RESOLUTION_RECORD_TYPE:
panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;

18
sys/dev/usb/if_axen.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: if_axen.c,v 1.33 2024/05/23 03:21:08 jsg Exp $ */
/* $OpenBSD: if_axen.c,v 1.34 2024/10/07 07:35:40 kevlo Exp $ */
/*
* Copyright (c) 2013 Yojiro UO <yuo@openbsd.org>
@ -17,7 +17,7 @@
*/
/*
* ASIX Electronics AX88178a USB 2.0 ethernet and
* ASIX Electronics AX88178a/AX88772d USB 2.0 ethernet and
* AX88179/AX88179a USB 3.0 Ethernet driver.
*/
@ -251,6 +251,8 @@ axen_miibus_statchg(struct device *dev)
sc->axen_link++;
break;
case IFM_1000_T:
if ((sc->axen_flags & AX772D) != 0)
break;
sc->axen_link++;
break;
default:
@ -658,8 +660,14 @@ axen_attach(struct device *parent, struct device *self, void *aux)
}
dd = usbd_get_device_descriptor(sc->axen_udev);
if (UGETW(dd->bcdDevice) == 0x200)
switch (UGETW(dd->bcdDevice)) {
case 0x200:
sc->axen_flags = AX179A;
break;
case 0x300:
sc->axen_flags = AX772D;
break;
}
s = splnet();
@ -683,6 +691,8 @@ axen_attach(struct device *parent, struct device *self, void *aux)
printf(" AX88178a");
else if (sc->axen_flags & AX179)
printf(" AX88179");
else if (sc->axen_flags & AX772D)
printf(" AX88772D");
else
printf(" AX88179A");
printf(", address %s\n", ether_sprintf(eaddr));
@ -968,7 +978,7 @@ axen_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status)
/* skip pseudo header (2byte) */
padlen = 2;
/* skip trailer padding (4Byte) for ax88179 */
if (!(sc->axen_flags & AX179A))
if (!(sc->axen_flags & (AX179A | AX772D)))
padlen += 4;
do {

3
sys/dev/usb/if_axenreg.h
View file

@ -1,4 +1,4 @@
/* $OpenBSD: if_axenreg.h,v 1.7 2024/01/04 08:41:59 kevlo Exp $ */
/* $OpenBSD: if_axenreg.h,v 1.8 2024/10/07 07:35:40 kevlo Exp $ */
/*
* Copyright (c) 2013 Yojiro UO <yuo@openbsd.org>. All right reserved.
@ -228,6 +228,7 @@ struct axen_type {
#define AX178A 0x0001 /* AX88178a */
#define AX179 0x0002 /* AX88179 */
#define AX179A 0x0004 /* AX88179a */
#define AX772D 0x0008 /* AX88772d */
};
struct axen_softc;

4
sys/dev/usb/usb_quirks.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: usb_quirks.c,v 1.79 2024/08/27 12:41:18 sthen Exp $ */
/* $OpenBSD: usb_quirks.c,v 1.80 2024/10/07 13:27:13 sthen Exp $ */
/* $NetBSD: usb_quirks.c,v 1.45 2003/05/10 17:47:14 hamajima Exp $ */
/* $FreeBSD: src/sys/dev/usb/usb_quirks.c,v 1.30 2003/01/02 04:15:55 imp Exp $ */
@ -154,6 +154,8 @@ const struct usbd_quirk_entry {
ANY, { UQ_MS_VENDOR_BUTTONS }},
/* Devices that need their data pipe held open */
{ USB_VENDOR_CHERRY, USB_PRODUCT_CHERRY_MOUSE1,
ANY, { UQ_ALWAYS_OPEN }},
{ USB_VENDOR_CHICONY, USB_PRODUCT_CHICONY_OPTMOUSE,
ANY, { UQ_ALWAYS_OPEN }},
{ USB_VENDOR_HAILUCK, USB_PRODUCT_HAILUCK_KEYBOARD,

3
sys/dev/usb/usbdevs
View file

@ -1,4 +1,4 @@
$OpenBSD: usbdevs,v 1.768 2024/08/27 12:31:18 sthen Exp $
$OpenBSD: usbdevs,v 1.769 2024/10/07 13:26:18 sthen Exp $
/* $NetBSD: usbdevs,v 1.322 2003/05/10 17:47:14 hamajima Exp $ */
/*
@ -1341,6 +1341,7 @@ product CHENSOURCE CM12402 0x933d CM12402 Eagle IR Cam
/* Cherry products */
product CHERRY MY3000KBD 0x0001 My3000 keyboard
product CHERRY MY3000HUB 0x0003 My3000 hub
product CHERRY MOUSE1 0xb091 mouse
/* Chic Technology products */
product CHIC MOUSE1 0x0001 mouse

5
sys/dev/usb/usbdevs.h
View file

@ -1,10 +1,10 @@
/* $OpenBSD: usbdevs.h,v 1.780 2024/08/27 12:31:43 sthen Exp $ */
/* $OpenBSD: usbdevs.h,v 1.781 2024/10/07 13:26:32 sthen Exp $ */
/*
* THIS FILE IS AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
* OpenBSD: usbdevs,v 1.768 2024/08/27 12:31:18 sthen Exp
* OpenBSD: usbdevs,v 1.769 2024/10/07 13:26:18 sthen Exp
*/
/* $NetBSD: usbdevs,v 1.322 2003/05/10 17:47:14 hamajima Exp $ */
@ -1348,6 +1348,7 @@
/* Cherry products */
#define USB_PRODUCT_CHERRY_MY3000KBD 0x0001 /* My3000 keyboard */
#define USB_PRODUCT_CHERRY_MY3000HUB 0x0003 /* My3000 hub */
#define USB_PRODUCT_CHERRY_MOUSE1 0xb091 /* mouse */
/* Chic Technology products */
#define USB_PRODUCT_CHIC_MOUSE1 0x0001 /* mouse */

8
sys/dev/usb/usbdevs_data.h
View file

@ -1,10 +1,10 @@
/* $OpenBSD: usbdevs_data.h,v 1.774 2024/08/27 12:31:43 sthen Exp $ */
/* $OpenBSD: usbdevs_data.h,v 1.775 2024/10/07 13:26:32 sthen Exp $ */
/*
* THIS FILE IS AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
* OpenBSD: usbdevs,v 1.768 2024/08/27 12:31:18 sthen Exp
* OpenBSD: usbdevs,v 1.769 2024/10/07 13:26:18 sthen Exp
*/
/* $NetBSD: usbdevs,v 1.322 2003/05/10 17:47:14 hamajima Exp $ */
@ -1929,6 +1929,10 @@ const struct usb_known_product usb_known_products[] = {
USB_VENDOR_CHERRY, USB_PRODUCT_CHERRY_MY3000HUB,
"My3000 hub",
},
{
USB_VENDOR_CHERRY, USB_PRODUCT_CHERRY_MOUSE1,
"mouse",
},
{
USB_VENDOR_CHIC, USB_PRODUCT_CHIC_MOUSE1,
"mouse",