59 lines
1.4 KiB
Text
59 lines
1.4 KiB
Text
Index: riscv/encoding.h
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--- riscv/encoding.h.orig
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+++ riscv/encoding.h
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@@ -221,55 +221,6 @@
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#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)
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-#ifdef __riscv
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-
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-#if __riscv_xlen == 64
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-# define MSTATUS_SD MSTATUS64_SD
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-# define SSTATUS_SD SSTATUS64_SD
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-# define RISCV_PGLEVEL_BITS 9
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-# define SATP_MODE SATP64_MODE
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-#else
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-# define MSTATUS_SD MSTATUS32_SD
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-# define SSTATUS_SD SSTATUS32_SD
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-# define RISCV_PGLEVEL_BITS 10
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-# define SATP_MODE SATP32_MODE
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-#endif
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-#define RISCV_PGSHIFT 12
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-#define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
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-
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-#ifndef __ASSEMBLER__
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-
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-#ifdef __GNUC__
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-
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-#define read_csr(reg) ({ unsigned long __tmp; \
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- asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
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- __tmp; })
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-
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-#define write_csr(reg, val) ({ \
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- asm volatile ("csrw " #reg ", %0" :: "rK"(val)); })
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-
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-#define swap_csr(reg, val) ({ unsigned long __tmp; \
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- asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \
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- __tmp; })
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-
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-#define set_csr(reg, bit) ({ unsigned long __tmp; \
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- asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \
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- __tmp; })
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-
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-#define clear_csr(reg, bit) ({ unsigned long __tmp; \
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- asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \
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- __tmp; })
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-
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-#define rdtime() read_csr(time)
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-#define rdcycle() read_csr(cycle)
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-#define rdinstret() read_csr(instret)
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-
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-#endif
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-
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-#endif
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-
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-#endif
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-
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#endif
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/* Automatically generated by parse_opcodes. */
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#ifndef RISCV_ENCODING_H
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