48 lines
2.2 KiB
Text
48 lines
2.2 KiB
Text
- Implement the 'h' register constraint on mips64. This lets clang build
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pieces of software that use the constraint if the compiler claims
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to be compatible with GCC 4.2.1.
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Note that the constraint was removed in GCC 4.4. The reason was that
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'h' could generate code whose result is unpredictable. The underlying
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reason is that the HI and LO registers are special, and the optimizer
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has to be careful when choosing the order of HI/LO accesses. It looks
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that LLVM has the needed logic.
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Index: lib/Target/Mips/MipsISelLowering.cpp
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--- lib/Target/Mips/MipsISelLowering.cpp.orig
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+++ lib/Target/Mips/MipsISelLowering.cpp
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@@ -3925,6 +3925,7 @@ MipsTargetLowering::getConstraintType(StringRef Constr
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// backwards compatibility.
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// 'c' : A register suitable for use in an indirect
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// jump. This will always be $25 for -mabicalls.
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+ // 'h' : The hi register. 1 word storage.
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// 'l' : The lo register. 1 word storage.
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// 'x' : The hilo register pair. Double word storage.
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if (Constraint.size() == 1) {
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@@ -3934,6 +3935,7 @@ MipsTargetLowering::getConstraintType(StringRef Constr
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case 'y':
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case 'f':
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case 'c':
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+ case 'h':
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case 'l':
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case 'x':
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return C_RegisterClass;
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@@ -3979,6 +3981,7 @@ MipsTargetLowering::getSingleConstraintMatchWeight(
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weight = CW_Register;
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break;
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case 'c': // $25 for indirect jumps
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+ case 'h': // hi register
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case 'l': // lo register
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case 'x': // hilo register pair
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if (type->isIntegerTy())
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@@ -4153,6 +4156,11 @@ MipsTargetLowering::getRegForInlineAsmConstraint(const
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return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass);
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// This will generate an error message
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return std::make_pair(0U, nullptr);
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+ case 'h': // use the `hi` register to store values
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+ // that are no bigger than a word
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+ if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8)
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+ return std::make_pair((unsigned)Mips::HI0, &Mips::HI32RegClass);
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+ return std::make_pair((unsigned)Mips::HI0_64, &Mips::HI64RegClass);
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case 'l': // use the `lo` register to store values
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// that are no bigger than a word
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if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8)
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