16 lines
817 B
Text
16 lines
817 B
Text
Yosys Open SYnthesis Suite
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Yosys is a framework for Verilog RTL synthesis. It currently has extensive
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Verilog-2005 support and provides a basic set of synthesis algorithms for
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various application domains. Selected features and typical applications:
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- Process almost any synthesizable Verilog-2005 design
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- Converting Verilog to BLIF / EDIF/ BTOR / SMT-LIB / simple RTL Verilog / etc.
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- Built-in formal methods for checking properties and equivalence
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- Mapping to ASIC standard cell libraries (in Liberty File Format)
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- Mapping to Xilinx 7-Series and Lattice iCE40 FPGAs
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- Foundation and/or front-end for custom flows
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Yosys can be adapted to perform any synthesis job by combining the existing
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passes (algorithms) using synthesis scripts and adding additional passes as
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needed by extending the Yosys C++ code base.
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