6 lines
424 B
Text
6 lines
424 B
Text
Verilator is the fastest free Verilog HDL simulator, and beats most
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commercial simulators. It compiles synthesizable Verilog (not test-bench
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code!), plus some PSL, SystemVerilog and Synthesis assertions into C++
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or SystemC code. It is designed for large projects where fast simulation
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performance is of primary concern, and is especially well suited to
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generate executable models of CPUs for embedded software design teams.
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