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This commit is contained in:
purplerain 2023-08-16 22:26:55 +00:00
commit 2c0afcbbf3
Signed by: purplerain
GPG key ID: F42C07F07E2E35B7
64331 changed files with 5339189 additions and 0 deletions
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155
devel/xtensa-esp32s3-elf/gcc/patches/patch-include_xtensa-config_h Normal file
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@ -0,0 +1,155 @@
xtensa-config.h for ESP32
Index: include/xtensa-config.h
--- include/xtensa-config.h.orig
+++ include/xtensa-config.h
@@ -1,5 +1,6 @@
/* Xtensa configuration settings.
- Copyright (C) 2001-2018 Free Software Foundation, Inc.
+ Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
+ Free Software Foundation, Inc.
Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica.
This program is free software; you can redistribute it and/or modify
@@ -25,7 +26,7 @@
macros. */
#undef XCHAL_HAVE_BE
-#define XCHAL_HAVE_BE 1
+#define XCHAL_HAVE_BE 0
#undef XCHAL_HAVE_DENSITY
#define XCHAL_HAVE_DENSITY 1
@@ -49,7 +50,7 @@
#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */
#undef XCHAL_HAVE_MAC16
-#define XCHAL_HAVE_MAC16 0
+#define XCHAL_HAVE_MAC16 1
#undef XCHAL_HAVE_MUL16
#define XCHAL_HAVE_MUL16 1
@@ -58,7 +59,7 @@
#define XCHAL_HAVE_MUL32 1
#undef XCHAL_HAVE_MUL32_HIGH
-#define XCHAL_HAVE_MUL32_HIGH 0
+#define XCHAL_HAVE_MUL32_HIGH 1
#undef XCHAL_HAVE_DIV32
#define XCHAL_HAVE_DIV32 1
@@ -85,30 +86,37 @@
#define XCHAL_HAVE_S32C1I 1
#undef XCHAL_HAVE_BOOLEANS
-#define XCHAL_HAVE_BOOLEANS 0
+#define XCHAL_HAVE_BOOLEANS 1
#undef XCHAL_HAVE_FP
-#define XCHAL_HAVE_FP 0
+#define XCHAL_HAVE_FP 1
#undef XCHAL_HAVE_FP_DIV
-#define XCHAL_HAVE_FP_DIV 0
+#define XCHAL_HAVE_FP_DIV 1
#undef XCHAL_HAVE_FP_RECIP
-#define XCHAL_HAVE_FP_RECIP 0
+#define XCHAL_HAVE_FP_RECIP 1
#undef XCHAL_HAVE_FP_SQRT
-#define XCHAL_HAVE_FP_SQRT 0
+#define XCHAL_HAVE_FP_SQRT 1
#undef XCHAL_HAVE_FP_RSQRT
-#define XCHAL_HAVE_FP_RSQRT 0
+#define XCHAL_HAVE_FP_RSQRT 1
+#undef XCHAL_HAVE_FP_POSTINC
+#define XCHAL_HAVE_FP_POSTINC 1
+
+#undef XCHAL_HAVE_DFP_ACCEL
+#define XCHAL_HAVE_DFP_ACCEL 0
+/* For backward compatibility */
#undef XCHAL_HAVE_DFP_accel
-#define XCHAL_HAVE_DFP_accel 0
+#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL
+
#undef XCHAL_HAVE_WINDOWED
#define XCHAL_HAVE_WINDOWED 1
#undef XCHAL_NUM_AREGS
-#define XCHAL_NUM_AREGS 32
+#define XCHAL_NUM_AREGS 64
#undef XCHAL_HAVE_WIDE_BRANCHES
#define XCHAL_HAVE_WIDE_BRANCHES 0
@@ -118,34 +126,31 @@
#undef XCHAL_ICACHE_SIZE
-#define XCHAL_ICACHE_SIZE 16384
+#define XCHAL_ICACHE_SIZE 0
#undef XCHAL_DCACHE_SIZE
-#define XCHAL_DCACHE_SIZE 16384
+#define XCHAL_DCACHE_SIZE 0
#undef XCHAL_ICACHE_LINESIZE
-#define XCHAL_ICACHE_LINESIZE 32
+#define XCHAL_ICACHE_LINESIZE 16
#undef XCHAL_DCACHE_LINESIZE
-#define XCHAL_DCACHE_LINESIZE 32
+#define XCHAL_DCACHE_LINESIZE 16
#undef XCHAL_ICACHE_LINEWIDTH
-#define XCHAL_ICACHE_LINEWIDTH 5
+#define XCHAL_ICACHE_LINEWIDTH 4
#undef XCHAL_DCACHE_LINEWIDTH
-#define XCHAL_DCACHE_LINEWIDTH 5
+#define XCHAL_DCACHE_LINEWIDTH 4
#undef XCHAL_DCACHE_IS_WRITEBACK
-#define XCHAL_DCACHE_IS_WRITEBACK 1
+#define XCHAL_DCACHE_IS_WRITEBACK 0
#undef XCHAL_HAVE_MMU
-#define XCHAL_HAVE_MMU 1
+#define XCHAL_HAVE_MMU 0
-#undef XCHAL_MMU_MIN_PTE_PAGE_SIZE
-#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12
-
#undef XCHAL_HAVE_DEBUG
#define XCHAL_HAVE_DEBUG 1
@@ -160,7 +165,7 @@
#undef XCHAL_MAX_INSTRUCTION_SIZE
-#define XCHAL_MAX_INSTRUCTION_SIZE 3
+#define XCHAL_MAX_INSTRUCTION_SIZE 4
#undef XCHAL_INST_FETCH_WIDTH
#define XCHAL_INST_FETCH_WIDTH 4
@@ -172,5 +177,16 @@
#define XSHAL_ABI XTHAL_ABI_WINDOWED
#define XTHAL_ABI_WINDOWED 0
#define XTHAL_ABI_CALL0 1
+
+
+#undef XCHAL_M_STAGE
+#define XCHAL_M_STAGE 2
+
+#undef XTENSA_MARCH_LATEST
+#define XTENSA_MARCH_LATEST 270012
+
+#undef XTENSA_MARCH_EARLIEST
+#define XTENSA_MARCH_EARLIEST 270012
+
#endif /* !XTENSA_CONFIG_H */