SecBSD/ports
2
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

SecBSD's official ports repository

Browse source
This commit is contained in:
purplerain 2023-08-16 22:26:55 +00:00
commit 2c0afcbbf3
Signed by: purplerain
GPG key ID: F42C07F07E2E35B7
64331 changed files with 5339189 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

31
devel/xtensa-esp32-elf/gdb/Makefile Normal file
View file

@ -0,0 +1,31 @@
COMMENT = gdb for ${CONFIG} cross-development
VERSION = 2.35.1.2021.2
PKGNAME = ${CONFIG}-gdb-${VERSION}
REVISION = 1
GH_ACCOUNT = espressif
GH_PROJECT = binutils-gdb
GH_TAGNAME = esp-2021r2-gdb
WANTLIB += ${COMPILER_LIBCXX} c curses expat m z
BUILD_DEPENDS = devel/libtool \
devel/bison \
devel/xtensa-esp32-elf/binutils
RUN_DEPENDS += devel/xtensa-esp32-elf/binutils
CONFIGURE_ARGS += --enable-commonbfdlib=no \
--with-cross-host=yes \
--disable-werror \
--without-guile \
--without-lzma \
--disable-binutils \
--disable-ld \
--disable-gas \
--disable-gprof \
--disable-install-libiberty \
--enable-gdb \
--enable-sim
.include <bsd.port.mk>

2
devel/xtensa-esp32-elf/gdb/distinfo Normal file
View file

@ -0,0 +1,2 @@
SHA256 (binutils-gdb-esp-2021r2-gdb.tar.gz) = FijYCbd4pYgHkw3rnGwxifr32CheWu9t9jvkFHyhhvg=
SIZE (binutils-gdb-esp-2021r2-gdb.tar.gz) = 59701067

26978
devel/xtensa-esp32-elf/gdb/patches/patch-bfd_xtensa-modules_c Normal file
View file

File diff suppressed because it is too large Load diff

14
devel/xtensa-esp32-elf/gdb/patches/patch-gdb_Makefile_in Normal file
View file

@ -0,0 +1,14 @@
Link mpfr dynamically
Index: gdb/Makefile.in
--- gdb/Makefile.in.orig
+++ gdb/Makefile.in
@@ -195,7 +195,7 @@ LIBBABELTRACE = @LIBBABELTRACE@
LIBIPT = @LIBIPT@
# Where is libmpfr? This will be empty if libmpfr was not available.
-LIBMPFR = @LIBMPFR@
+LIBMPFR = @LTLIBMPFR@
WARN_CFLAGS = @WARN_CFLAGS@
WERROR_CFLAGS = @WERROR_CFLAGS@

77
devel/xtensa-esp32-elf/gdb/patches/patch-gdb_gdbserver_xtensa-regmap_c Normal file
View file

@ -0,0 +1,77 @@
New file from espressif overlays.
Index: gdb/gdbserver/xtensa-regmap.c
--- gdb/gdbserver/xtensa-regmap.c.orig
+++ gdb/gdbserver/xtensa-regmap.c
@@ -0,0 +1,71 @@
+/* Customized table mapping between kernel xtregset and GDB register cache.
+
+ Copyright (c) 2007-2010 Tensilica Inc.
+
+ Permission is hereby granted, free of charge, to any person obtaining
+ a copy of this software and associated documentation files (the
+ "Software"), to deal in the Software without restriction, including
+ without limitation the rights to use, copy, modify, merge, publish,
+ distribute, sublicense, and/or sell copies of the Software, and to
+ permit persons to whom the Software is furnished to do so, subject to
+ the following conditions:
+
+ The above copyright notice and this permission notice shall be included
+ in all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+
+typedef struct {
+ int gdb_regnum;
+ int gdb_offset;
+ int ptrace_cp_offset;
+ int ptrace_offset;
+ int size;
+ int coproc;
+ int dbnum;
+ char* name
+;} xtensa_regtable_t;
+
+#define XTENSA_ELF_XTREG_SIZE 116
+
+const xtensa_regtable_t xtensa_regmap_table[] = {
+ /* gnum,gofs,cpofs,ofs,siz,cp, dbnum, name */
+ { 75, 300, 8, 8, 4, -1, 0x0204, "br" },
+ { 76, 304, 12, 12, 4, -1, 0x020c, "scompare1" },
+ { 77, 308, 0, 0, 4, -1, 0x0210, "acclo" },
+ { 78, 312, 4, 4, 4, -1, 0x0211, "acchi" },
+ { 79, 316, 16, 16, 4, -1, 0x0220, "m0" },
+ { 80, 320, 20, 20, 4, -1, 0x0221, "m1" },
+ { 81, 324, 24, 24, 4, -1, 0x0222, "m2" },
+ { 82, 328, 28, 28, 4, -1, 0x0223, "m3" },
+ { 84, 336, 32, 32, 4, -1, 0x03ea, "f64r_lo" },
+ { 85, 340, 36, 36, 4, -1, 0x03eb, "f64r_hi" },
+ { 86, 344, 40, 40, 4, -1, 0x03ec, "f64s" },
+ { 87, 348, 8, 52, 4, 0, 0x0030, "f0" },
+ { 88, 352, 12, 56, 4, 0, 0x0031, "f1" },
+ { 89, 356, 16, 60, 4, 0, 0x0032, "f2" },
+ { 90, 360, 20, 64, 4, 0, 0x0033, "f3" },
+ { 91, 364, 24, 68, 4, 0, 0x0034, "f4" },
+ { 92, 368, 28, 72, 4, 0, 0x0035, "f5" },
+ { 93, 372, 32, 76, 4, 0, 0x0036, "f6" },
+ { 94, 376, 36, 80, 4, 0, 0x0037, "f7" },
+ { 95, 380, 40, 84, 4, 0, 0x0038, "f8" },
+ { 96, 384, 44, 88, 4, 0, 0x0039, "f9" },
+ { 97, 388, 48, 92, 4, 0, 0x003a, "f10" },
+ { 98, 392, 52, 96, 4, 0, 0x003b, "f11" },
+ { 99, 396, 56, 100, 4, 0, 0x003c, "f12" },
+ { 100, 400, 60, 104, 4, 0, 0x003d, "f13" },
+ { 101, 404, 64, 108, 4, 0, 0x003e, "f14" },
+ { 102, 408, 68, 112, 4, 0, 0x003f, "f15" },
+ { 103, 412, 0, 44, 4, 0, 0x03e8, "fcr" },
+ { 104, 416, 4, 48, 4, 0, 0x03e9, "fsr" },
+ { 0 }
+};
+

84
devel/xtensa-esp32-elf/gdb/patches/patch-gdb_gdbserver_xtensa-xtregs_c Normal file
View file

@ -0,0 +1,84 @@
Index: gdb/gdbserver/xtensa-xtregs.c
--- gdb/gdbserver/xtensa-xtregs.c.orig
+++ gdb/gdbserver/xtensa-xtregs.c
@@ -1,20 +1,25 @@
-/* Table mapping between kernel xtregset and GDB register cache.
- Copyright (C) 2007-2020 Free Software Foundation, Inc.
+/* Customized table mapping between kernel xtregset and GDB register cache.
- This file is part of GDB.
+ Copyright (c) 2007-2010 Tensilica Inc.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 3 of the
- License, or (at your option) any later version.
+ Permission is hereby granted, free of charge, to any person obtaining
+ a copy of this software and associated documentation files (the
+ "Software"), to deal in the Software without restriction, including
+ without limitation the rights to use, copy, modify, merge, publish,
+ distribute, sublicense, and/or sell copies of the Software, and to
+ permit persons to whom the Software is furnished to do so, subject to
+ the following conditions:
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- General Public License for more details.
+ The above copyright notice and this permission notice shall be included
+ in all copies or substantial portions of the Software.
- You should have received a copy of the GNU General Public License
- along with this program. If not, see <http://www.gnu.org/licenses/>. */
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
typedef struct {
@@ -28,10 +33,39 @@ typedef struct {
char* name
;} xtensa_regtable_t;
-#define XTENSA_ELF_XTREG_SIZE 4
+#define XTENSA_ELF_XTREG_SIZE 116
const xtensa_regtable_t xtensa_regmap_table[] = {
/* gnum,gofs,cpofs,ofs,siz,cp, dbnum, name */
- { 44, 176, 0, 0, 4, -1, 0x020c, "scompare1" },
+ { 75, 300, 8, 8, 4, -1, 0x0204, "br" },
+ { 76, 304, 12, 12, 4, -1, 0x020c, "scompare1" },
+ { 77, 308, 0, 0, 4, -1, 0x0210, "acclo" },
+ { 78, 312, 4, 4, 4, -1, 0x0211, "acchi" },
+ { 79, 316, 16, 16, 4, -1, 0x0220, "m0" },
+ { 80, 320, 20, 20, 4, -1, 0x0221, "m1" },
+ { 81, 324, 24, 24, 4, -1, 0x0222, "m2" },
+ { 82, 328, 28, 28, 4, -1, 0x0223, "m3" },
+ { 84, 336, 32, 32, 4, -1, 0x03ea, "f64r_lo" },
+ { 85, 340, 36, 36, 4, -1, 0x03eb, "f64r_hi" },
+ { 86, 344, 40, 40, 4, -1, 0x03ec, "f64s" },
+ { 87, 348, 8, 52, 4, 0, 0x0030, "f0" },
+ { 88, 352, 12, 56, 4, 0, 0x0031, "f1" },
+ { 89, 356, 16, 60, 4, 0, 0x0032, "f2" },
+ { 90, 360, 20, 64, 4, 0, 0x0033, "f3" },
+ { 91, 364, 24, 68, 4, 0, 0x0034, "f4" },
+ { 92, 368, 28, 72, 4, 0, 0x0035, "f5" },
+ { 93, 372, 32, 76, 4, 0, 0x0036, "f6" },
+ { 94, 376, 36, 80, 4, 0, 0x0037, "f7" },
+ { 95, 380, 40, 84, 4, 0, 0x0038, "f8" },
+ { 96, 384, 44, 88, 4, 0, 0x0039, "f9" },
+ { 97, 388, 48, 92, 4, 0, 0x003a, "f10" },
+ { 98, 392, 52, 96, 4, 0, 0x003b, "f11" },
+ { 99, 396, 56, 100, 4, 0, 0x003c, "f12" },
+ { 100, 400, 60, 104, 4, 0, 0x003d, "f13" },
+ { 101, 404, 64, 108, 4, 0, 0x003e, "f14" },
+ { 102, 408, 68, 112, 4, 0, 0x003f, "f15" },
+ { 103, 412, 0, 44, 4, 0, 0x03e8, "fcr" },
+ { 104, 416, 4, 48, 4, 0, 0x03e9, "fsr" },
{ 0 }
};
+

82
devel/xtensa-esp32-elf/gdb/patches/patch-gdb_regformats_reg-xtensa_dat Normal file
View file

@ -0,0 +1,82 @@
Index: gdb/regformats/reg-xtensa.dat
--- gdb/regformats/reg-xtensa.dat.orig
+++ gdb/regformats/reg-xtensa.dat
@@ -33,15 +33,75 @@ expedite:pc,windowbase,windowstart
32:ar29
32:ar30
32:ar31
+32:ar32
+32:ar33
+32:ar34
+32:ar35
+32:ar36
+32:ar37
+32:ar38
+32:ar39
+32:ar40
+32:ar41
+32:ar42
+32:ar43
+32:ar44
+32:ar45
+32:ar46
+32:ar47
+32:ar48
+32:ar49
+32:ar50
+32:ar51
+32:ar52
+32:ar53
+32:ar54
+32:ar55
+32:ar56
+32:ar57
+32:ar58
+32:ar59
+32:ar60
+32:ar61
+32:ar62
+32:ar63
32:lbeg
32:lend
32:lcount
32:sar
-32:litbase
32:windowbase
32:windowstart
-32:sr176
-32:sr208
+32:configid0
+32:configid1
32:ps
32:threadptr
+32:br
32:scompare1
+32:acclo
+32:acchi
+32:m0
+32:m1
+32:m2
+32:m3
+32:expstate
+32:f64r_lo
+32:f64r_hi
+32:f64s
+32:f0
+32:f1
+32:f2
+32:f3
+32:f4
+32:f5
+32:f6
+32:f7
+32:f8
+32:f9
+32:f10
+32:f11
+32:f12
+32:f13
+32:f14
+32:f15
+32:fcr
+32:fsr

494
devel/xtensa-esp32-elf/gdb/patches/patch-gdb_xtensa-config_c Normal file
View file

@ -0,0 +1,494 @@
Index: gdb/xtensa-config.c
--- gdb/xtensa-config.c.orig
+++ gdb/xtensa-config.c
@@ -1,64 +1,115 @@
/* Configuration for the Xtensa architecture for GDB, the GNU debugger.
- Copyright (C) 2003-2020 Free Software Foundation, Inc.
+ Copyright (c) 2003-2016 Tensilica Inc.
- This file is part of GDB.
+ Permission is hereby granted, free of charge, to any person obtaining
+ a copy of this software and associated documentation files (the
+ "Software"), to deal in the Software without restriction, including
+ without limitation the rights to use, copy, modify, merge, publish,
+ distribute, sublicense, and/or sell copies of the Software, and to
+ permit persons to whom the Software is furnished to do so, subject to
+ the following conditions:
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
+ The above copyright notice and this permission notice shall be included
+ in all copies or substantial portions of the Software.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
- You should have received a copy of the GNU General Public License
- along with this program. If not, see <http://www.gnu.org/licenses/>. */
-
-#include "defs.h"
-
#define XTENSA_CONFIG_VERSION 0x60
+#include "defs.h"
#include "xtensa-config.h"
#include "xtensa-tdep.h"
/* Masked registers. */
-xtensa_reg_mask_t xtensa_submask0[] = { { 42, 0, 4 } };
+xtensa_reg_mask_t xtensa_submask0[] = { { 75, 0, 1 } };
const xtensa_mask_t xtensa_mask0 = { 1, xtensa_submask0 };
-xtensa_reg_mask_t xtensa_submask1[] = { { 42, 5, 1 } };
+xtensa_reg_mask_t xtensa_submask1[] = { { 75, 1, 1 } };
const xtensa_mask_t xtensa_mask1 = { 1, xtensa_submask1 };
-xtensa_reg_mask_t xtensa_submask2[] = { { 42, 18, 1 } };
+xtensa_reg_mask_t xtensa_submask2[] = { { 75, 2, 1 } };
const xtensa_mask_t xtensa_mask2 = { 1, xtensa_submask2 };
-xtensa_reg_mask_t xtensa_submask3[] = { { 42, 6, 2 } };
+xtensa_reg_mask_t xtensa_submask3[] = { { 75, 3, 1 } };
const xtensa_mask_t xtensa_mask3 = { 1, xtensa_submask3 };
-xtensa_reg_mask_t xtensa_submask4[] = { { 42, 4, 1 } };
+xtensa_reg_mask_t xtensa_submask4[] = { { 75, 4, 1 } };
const xtensa_mask_t xtensa_mask4 = { 1, xtensa_submask4 };
-xtensa_reg_mask_t xtensa_submask5[] = { { 42, 16, 2 } };
+xtensa_reg_mask_t xtensa_submask5[] = { { 75, 5, 1 } };
const xtensa_mask_t xtensa_mask5 = { 1, xtensa_submask5 };
-xtensa_reg_mask_t xtensa_submask6[] = { { 42, 8, 4 } };
+xtensa_reg_mask_t xtensa_submask6[] = { { 75, 6, 1 } };
const xtensa_mask_t xtensa_mask6 = { 1, xtensa_submask6 };
-xtensa_reg_mask_t xtensa_submask7[] = { { 37, 12, 20 } };
+xtensa_reg_mask_t xtensa_submask7[] = { { 75, 7, 1 } };
const xtensa_mask_t xtensa_mask7 = { 1, xtensa_submask7 };
-xtensa_reg_mask_t xtensa_submask8[] = { { 37, 0, 1 } };
+xtensa_reg_mask_t xtensa_submask8[] = { { 75, 8, 1 } };
const xtensa_mask_t xtensa_mask8 = { 1, xtensa_submask8 };
-xtensa_reg_mask_t xtensa_submask9[] = { { 86, 8, 4 } };
+xtensa_reg_mask_t xtensa_submask9[] = { { 75, 9, 1 } };
const xtensa_mask_t xtensa_mask9 = { 1, xtensa_submask9 };
-xtensa_reg_mask_t xtensa_submask10[] = { { 47, 24, 8 } };
+xtensa_reg_mask_t xtensa_submask10[] = { { 75, 10, 1 } };
const xtensa_mask_t xtensa_mask10 = { 1, xtensa_submask10 };
-xtensa_reg_mask_t xtensa_submask11[] = { { 47, 16, 8 } };
+xtensa_reg_mask_t xtensa_submask11[] = { { 75, 11, 1 } };
const xtensa_mask_t xtensa_mask11 = { 1, xtensa_submask11 };
-xtensa_reg_mask_t xtensa_submask12[] = { { 47, 8, 8 } };
+xtensa_reg_mask_t xtensa_submask12[] = { { 75, 12, 1 } };
const xtensa_mask_t xtensa_mask12 = { 1, xtensa_submask12 };
-xtensa_reg_mask_t xtensa_submask13[] = { { 48, 16, 2 } };
+xtensa_reg_mask_t xtensa_submask13[] = { { 75, 13, 1 } };
const xtensa_mask_t xtensa_mask13 = { 1, xtensa_submask13 };
-xtensa_reg_mask_t xtensa_submask14[] = { { 49, 16, 2 } };
+xtensa_reg_mask_t xtensa_submask14[] = { { 75, 14, 1 } };
const xtensa_mask_t xtensa_mask14 = { 1, xtensa_submask14 };
-xtensa_reg_mask_t xtensa_submask15[] = { { 45, 22, 10 } };
+xtensa_reg_mask_t xtensa_submask15[] = { { 75, 15, 1 } };
const xtensa_mask_t xtensa_mask15 = { 1, xtensa_submask15 };
+xtensa_reg_mask_t xtensa_submask16[] = { { 73, 0, 4 } };
+const xtensa_mask_t xtensa_mask16 = { 1, xtensa_submask16 };
+xtensa_reg_mask_t xtensa_submask17[] = { { 73, 5, 1 } };
+const xtensa_mask_t xtensa_mask17 = { 1, xtensa_submask17 };
+xtensa_reg_mask_t xtensa_submask18[] = { { 73, 18, 1 } };
+const xtensa_mask_t xtensa_mask18 = { 1, xtensa_submask18 };
+xtensa_reg_mask_t xtensa_submask19[] = { { 73, 4, 1 } };
+const xtensa_mask_t xtensa_mask19 = { 1, xtensa_submask19 };
+xtensa_reg_mask_t xtensa_submask20[] = { { 73, 16, 2 } };
+const xtensa_mask_t xtensa_mask20 = { 1, xtensa_submask20 };
+xtensa_reg_mask_t xtensa_submask21[] = { { 73, 8, 4 } };
+const xtensa_mask_t xtensa_mask21 = { 1, xtensa_submask21 };
+xtensa_reg_mask_t xtensa_submask22[] = { { 77, 0, 32 }, { 78, 0, 8 } };
+const xtensa_mask_t xtensa_mask22 = { 2, xtensa_submask22 };
+xtensa_reg_mask_t xtensa_submask23[] = { { 144, 8, 4 } };
+const xtensa_mask_t xtensa_mask23 = { 1, xtensa_submask23 };
+xtensa_reg_mask_t xtensa_submask24[] = { { 84, 0, 32 }, { 85, 0, 32 } };
+const xtensa_mask_t xtensa_mask24 = { 2, xtensa_submask24 };
+xtensa_reg_mask_t xtensa_submask25[] = { { 103, 0, 2 } };
+const xtensa_mask_t xtensa_mask25 = { 1, xtensa_submask25 };
+xtensa_reg_mask_t xtensa_submask26[] = { { 103, 6, 1 } };
+const xtensa_mask_t xtensa_mask26 = { 1, xtensa_submask26 };
+xtensa_reg_mask_t xtensa_submask27[] = { { 103, 5, 1 } };
+const xtensa_mask_t xtensa_mask27 = { 1, xtensa_submask27 };
+xtensa_reg_mask_t xtensa_submask28[] = { { 103, 4, 1 } };
+const xtensa_mask_t xtensa_mask28 = { 1, xtensa_submask28 };
+xtensa_reg_mask_t xtensa_submask29[] = { { 103, 3, 1 } };
+const xtensa_mask_t xtensa_mask29 = { 1, xtensa_submask29 };
+xtensa_reg_mask_t xtensa_submask30[] = { { 103, 2, 1 } };
+const xtensa_mask_t xtensa_mask30 = { 1, xtensa_submask30 };
+xtensa_reg_mask_t xtensa_submask31[] = { { 104, 11, 1 } };
+const xtensa_mask_t xtensa_mask31 = { 1, xtensa_submask31 };
+xtensa_reg_mask_t xtensa_submask32[] = { { 104, 10, 1 } };
+const xtensa_mask_t xtensa_mask32 = { 1, xtensa_submask32 };
+xtensa_reg_mask_t xtensa_submask33[] = { { 104, 9, 1 } };
+const xtensa_mask_t xtensa_mask33 = { 1, xtensa_submask33 };
+xtensa_reg_mask_t xtensa_submask34[] = { { 104, 8, 1 } };
+const xtensa_mask_t xtensa_mask34 = { 1, xtensa_submask34 };
+xtensa_reg_mask_t xtensa_submask35[] = { { 104, 7, 1 } };
+const xtensa_mask_t xtensa_mask35 = { 1, xtensa_submask35 };
+xtensa_reg_mask_t xtensa_submask36[] = { { 103, 12, 20 } };
+const xtensa_mask_t xtensa_mask36 = { 1, xtensa_submask36 };
+xtensa_reg_mask_t xtensa_submask37[] = { { 104, 12, 20 } };
+const xtensa_mask_t xtensa_mask37 = { 1, xtensa_submask37 };
+xtensa_reg_mask_t xtensa_submask38[] = { { 103, 7, 5 } };
+const xtensa_mask_t xtensa_mask38 = { 1, xtensa_submask38 };
+xtensa_reg_mask_t xtensa_submask39[] = { { 104, 0, 7 } };
+const xtensa_mask_t xtensa_mask39 = { 1, xtensa_submask39 };
/* Register map. */
@@ -98,124 +149,246 @@ xtensa_register_t rmap[] =
XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0)
XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0)
XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0)
- XTREG( 33,132,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0)
- XTREG( 34,136,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0)
- XTREG( 35,140,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0)
- XTREG( 36,144, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0)
- XTREG( 37,148,32, 4, 4,0x0205,0x0006,-2, 2,0x1100,litbase, 0,0,0,0,0,0)
- XTREG( 38,152, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0)
- XTREG( 39,156, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0)
- XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,sr176, 0,0,0,0,0,0)
- XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,sr208, 0,0,0,0,0,0)
- XTREG( 42,168,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0)
- XTREG( 43,172,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr, 0,0,0,0,0,0)
- XTREG( 44,176,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0)
- XTREG( 45,180,32, 4, 4,0x0253,0x0007,-2, 2,0x1000,ptevaddr, 0,0,0,0,0,0)
- XTREG( 46,184,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, 0,0,0,0,0,0)
- XTREG( 47,188,32, 4, 4,0x025a,0x0007,-2, 2,0x1000,rasid, 0,0,0,0,0,0)
- XTREG( 48,192,18, 4, 4,0x025b,0x0007,-2, 2,0x1000,itlbcfg, 0,0,0,0,0,0)
- XTREG( 49,196,18, 4, 4,0x025c,0x0007,-2, 2,0x1000,dtlbcfg, 0,0,0,0,0,0)
- XTREG( 50,200, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0)
- XTREG( 51,204,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0)
- XTREG( 52,208,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0)
- XTREG( 53,212,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0)
- XTREG( 54,216,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0)
- XTREG( 55,220,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0)
- XTREG( 56,224,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0)
- XTREG( 57,228,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0)
- XTREG( 58,232,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0)
- XTREG( 59,236,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0)
- XTREG( 60,240,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0)
- XTREG( 61,244,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0)
- XTREG( 62,248,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0)
- XTREG( 63,252,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, 0,0,0,0,0,0)
- XTREG( 64,256,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7, 0,0,0,0,0,0)
- XTREG( 65,260,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0)
- XTREG( 66,264,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0)
- XTREG( 67,268,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0)
- XTREG( 68,272,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0)
- XTREG( 69,276,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, 0,0,0,0,0,0)
- XTREG( 70,280,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, 0,0,0,0,0,0)
- XTREG( 71,284,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7, 0,0,0,0,0,0)
- XTREG( 72,288,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0)
- XTREG( 73,292,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0)
- XTREG( 74,296,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0)
- XTREG( 75,300,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0)
- XTREG( 76,304,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, 0,0,0,0,0,0)
- XTREG( 77,308,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, 0,0,0,0,0,0)
- XTREG( 78,312,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7, 0,0,0,0,0,0)
- XTREG( 79,316, 8, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable, 0,0,0,0,0,0)
- XTREG( 80,320,22, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0)
- XTREG( 81,324,22, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0)
- XTREG( 82,328,22, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0)
- XTREG( 83,332,22, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0)
- XTREG( 84,336,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
- XTREG( 85,340, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0)
- XTREG( 86,344,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0)
- XTREG( 87,348,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0)
- XTREG( 88,352,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0)
- XTREG( 89,356,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0)
- XTREG( 90,360, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0)
- XTREG( 91,364,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0)
- XTREG( 92,368,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0)
- XTREG( 93,372,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0)
- XTREG( 94,376,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2, 0,0,0,0,0,0)
- XTREG( 95,380,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0)
- XTREG( 96,384,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0)
- XTREG( 97,388,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0)
- XTREG( 98,392,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0)
- XTREG( 99,396,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0)
- XTREG(100,400,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0)
- XTREG(101,404,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0)
- XTREG(102,408,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0)
- XTREG(103,412,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0)
- XTREG(104,416,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0)
- XTREG(105,420,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0)
- XTREG(106,424,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0)
- XTREG(107,428,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, 0,0,0,0,0,0)
- XTREG(108,432,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, 0,0,0,0,0,0)
- XTREG(109,436,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, 0,0,0,0,0,0)
- XTREG(110,440,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0)
- XTREG(111,444,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0)
- XTREG(112,448,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0)
- XTREG(113,452, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel,
+ XTREG( 33,132,32, 4, 4,0x0120,0x0006,-2, 1,0x0002,ar32, 0,0,0,0,0,0)
+ XTREG( 34,136,32, 4, 4,0x0121,0x0006,-2, 1,0x0002,ar33, 0,0,0,0,0,0)
+ XTREG( 35,140,32, 4, 4,0x0122,0x0006,-2, 1,0x0002,ar34, 0,0,0,0,0,0)
+ XTREG( 36,144,32, 4, 4,0x0123,0x0006,-2, 1,0x0002,ar35, 0,0,0,0,0,0)
+ XTREG( 37,148,32, 4, 4,0x0124,0x0006,-2, 1,0x0002,ar36, 0,0,0,0,0,0)
+ XTREG( 38,152,32, 4, 4,0x0125,0x0006,-2, 1,0x0002,ar37, 0,0,0,0,0,0)
+ XTREG( 39,156,32, 4, 4,0x0126,0x0006,-2, 1,0x0002,ar38, 0,0,0,0,0,0)
+ XTREG( 40,160,32, 4, 4,0x0127,0x0006,-2, 1,0x0002,ar39, 0,0,0,0,0,0)
+ XTREG( 41,164,32, 4, 4,0x0128,0x0006,-2, 1,0x0002,ar40, 0,0,0,0,0,0)
+ XTREG( 42,168,32, 4, 4,0x0129,0x0006,-2, 1,0x0002,ar41, 0,0,0,0,0,0)
+ XTREG( 43,172,32, 4, 4,0x012a,0x0006,-2, 1,0x0002,ar42, 0,0,0,0,0,0)
+ XTREG( 44,176,32, 4, 4,0x012b,0x0006,-2, 1,0x0002,ar43, 0,0,0,0,0,0)
+ XTREG( 45,180,32, 4, 4,0x012c,0x0006,-2, 1,0x0002,ar44, 0,0,0,0,0,0)
+ XTREG( 46,184,32, 4, 4,0x012d,0x0006,-2, 1,0x0002,ar45, 0,0,0,0,0,0)
+ XTREG( 47,188,32, 4, 4,0x012e,0x0006,-2, 1,0x0002,ar46, 0,0,0,0,0,0)
+ XTREG( 48,192,32, 4, 4,0x012f,0x0006,-2, 1,0x0002,ar47, 0,0,0,0,0,0)
+ XTREG( 49,196,32, 4, 4,0x0130,0x0006,-2, 1,0x0002,ar48, 0,0,0,0,0,0)
+ XTREG( 50,200,32, 4, 4,0x0131,0x0006,-2, 1,0x0002,ar49, 0,0,0,0,0,0)
+ XTREG( 51,204,32, 4, 4,0x0132,0x0006,-2, 1,0x0002,ar50, 0,0,0,0,0,0)
+ XTREG( 52,208,32, 4, 4,0x0133,0x0006,-2, 1,0x0002,ar51, 0,0,0,0,0,0)
+ XTREG( 53,212,32, 4, 4,0x0134,0x0006,-2, 1,0x0002,ar52, 0,0,0,0,0,0)
+ XTREG( 54,216,32, 4, 4,0x0135,0x0006,-2, 1,0x0002,ar53, 0,0,0,0,0,0)
+ XTREG( 55,220,32, 4, 4,0x0136,0x0006,-2, 1,0x0002,ar54, 0,0,0,0,0,0)
+ XTREG( 56,224,32, 4, 4,0x0137,0x0006,-2, 1,0x0002,ar55, 0,0,0,0,0,0)
+ XTREG( 57,228,32, 4, 4,0x0138,0x0006,-2, 1,0x0002,ar56, 0,0,0,0,0,0)
+ XTREG( 58,232,32, 4, 4,0x0139,0x0006,-2, 1,0x0002,ar57, 0,0,0,0,0,0)
+ XTREG( 59,236,32, 4, 4,0x013a,0x0006,-2, 1,0x0002,ar58, 0,0,0,0,0,0)
+ XTREG( 60,240,32, 4, 4,0x013b,0x0006,-2, 1,0x0002,ar59, 0,0,0,0,0,0)
+ XTREG( 61,244,32, 4, 4,0x013c,0x0006,-2, 1,0x0002,ar60, 0,0,0,0,0,0)
+ XTREG( 62,248,32, 4, 4,0x013d,0x0006,-2, 1,0x0002,ar61, 0,0,0,0,0,0)
+ XTREG( 63,252,32, 4, 4,0x013e,0x0006,-2, 1,0x0002,ar62, 0,0,0,0,0,0)
+ XTREG( 64,256,32, 4, 4,0x013f,0x0006,-2, 1,0x0002,ar63, 0,0,0,0,0,0)
+ XTREG( 65,260,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0)
+ XTREG( 66,264,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0)
+ XTREG( 67,268,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0)
+ XTREG( 68,272, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0)
+ XTREG( 69,276, 4, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0)
+ XTREG( 70,280,16, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0)
+ XTREG( 71,284,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, 0,0,0,0,0,0)
+ XTREG( 72,288,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, 0,0,0,0,0,0)
+ XTREG( 73,292,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0)
+ XTREG( 74,296,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr, 0,0,0,0,0,0)
+ XTREG( 75,300,16, 4, 4,0x0204,0x0006,-1, 2,0x1100,br, 0,0,0,0,0,0)
+ XTREG( 76,304,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0)
+ XTREG( 77,308,32, 4, 4,0x0210,0x0006,-1, 2,0x1100,acclo, 0,0,0,0,0,0)
+ XTREG( 78,312, 8, 4, 4,0x0211,0x0006,-1, 2,0x1100,acchi, 0,0,0,0,0,0)
+ XTREG( 79,316,32, 4, 4,0x0220,0x0006,-1, 2,0x1100,m0, 0,0,0,0,0,0)
+ XTREG( 80,320,32, 4, 4,0x0221,0x0006,-1, 2,0x1100,m1, 0,0,0,0,0,0)
+ XTREG( 81,324,32, 4, 4,0x0222,0x0006,-1, 2,0x1100,m2, 0,0,0,0,0,0)
+ XTREG( 82,328,32, 4, 4,0x0223,0x0006,-1, 2,0x1100,m3, 0,0,0,0,0,0)
+ XTREG( 83,332,32, 4, 4,0x03e6,0x000e,-1, 3,0x0110,expstate, 0,0,0,0,0,0)
+ XTREG( 84,336,32, 4, 4,0x03ea,0x0006,-1, 3,0x0100,f64r_lo, 0,0,0,0,0,0)
+ XTREG( 85,340,32, 4, 4,0x03eb,0x0006,-1, 3,0x0100,f64r_hi, 0,0,0,0,0,0)
+ XTREG( 86,344,32, 4, 4,0x03ec,0x0006,-1, 3,0x0110,f64s, 0,0,0,0,0,0)
+ XTREG( 87,348,32, 4, 4,0x0030,0x0006, 0, 4,0x0401,f0,
+ "03:03:44:00","03:03:04:00",0,0,0,0)
+ XTREG( 88,352,32, 4, 4,0x0031,0x0006, 0, 4,0x0401,f1,
+ "03:13:44:00","03:13:04:00",0,0,0,0)
+ XTREG( 89,356,32, 4, 4,0x0032,0x0006, 0, 4,0x0401,f2,
+ "03:23:44:00","03:23:04:00",0,0,0,0)
+ XTREG( 90,360,32, 4, 4,0x0033,0x0006, 0, 4,0x0401,f3,
+ "03:33:44:00","03:33:04:00",0,0,0,0)
+ XTREG( 91,364,32, 4, 4,0x0034,0x0006, 0, 4,0x0401,f4,
+ "03:43:44:00","03:43:04:00",0,0,0,0)
+ XTREG( 92,368,32, 4, 4,0x0035,0x0006, 0, 4,0x0401,f5,
+ "03:53:44:00","03:53:04:00",0,0,0,0)
+ XTREG( 93,372,32, 4, 4,0x0036,0x0006, 0, 4,0x0401,f6,
+ "03:63:44:00","03:63:04:00",0,0,0,0)
+ XTREG( 94,376,32, 4, 4,0x0037,0x0006, 0, 4,0x0401,f7,
+ "03:73:44:00","03:73:04:00",0,0,0,0)
+ XTREG( 95,380,32, 4, 4,0x0038,0x0006, 0, 4,0x0401,f8,
+ "03:83:44:00","03:83:04:00",0,0,0,0)
+ XTREG( 96,384,32, 4, 4,0x0039,0x0006, 0, 4,0x0401,f9,
+ "03:93:44:00","03:93:04:00",0,0,0,0)
+ XTREG( 97,388,32, 4, 4,0x003a,0x0006, 0, 4,0x0401,f10,
+ "03:a3:44:00","03:a3:04:00",0,0,0,0)
+ XTREG( 98,392,32, 4, 4,0x003b,0x0006, 0, 4,0x0401,f11,
+ "03:b3:44:00","03:b3:04:00",0,0,0,0)
+ XTREG( 99,396,32, 4, 4,0x003c,0x0006, 0, 4,0x0401,f12,
+ "03:c3:44:00","03:c3:04:00",0,0,0,0)
+ XTREG(100,400,32, 4, 4,0x003d,0x0006, 0, 4,0x0401,f13,
+ "03:d3:44:00","03:d3:04:00",0,0,0,0)
+ XTREG(101,404,32, 4, 4,0x003e,0x0006, 0, 4,0x0401,f14,
+ "03:e3:44:00","03:e3:04:00",0,0,0,0)
+ XTREG(102,408,32, 4, 4,0x003f,0x0006, 0, 4,0x0401,f15,
+ "03:f3:44:00","03:f3:04:00",0,0,0,0)
+ XTREG(103,412,32, 4, 4,0x03e8,0x0006, 0, 3,0x0100,fcr, 0,0,0,0,0,0)
+ XTREG(104,416,32, 4, 4,0x03e9,0x0006, 0, 3,0x0100,fsr, 0,0,0,0,0,0)
+ XTREG(105,420,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, 0,0,0,0,0,0)
+ XTREG(106,424, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0)
+ XTREG(107,428, 1, 4, 4,0x0261,0x0007,-2, 2,0x1000,memctl, 0,0,0,0,0,0)
+ XTREG(108,432, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0)
+ XTREG(109,436,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0)
+ XTREG(110,440,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0)
+ XTREG(111,444,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0)
+ XTREG(112,448,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0)
+ XTREG(113,452,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0)
+ XTREG(114,456,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0)
+ XTREG(115,460,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0)
+ XTREG(116,464,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0)
+ XTREG(117,468,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0)
+ XTREG(118,472,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0)
+ XTREG(119,476,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0)
+ XTREG(120,480,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0)
+ XTREG(121,484,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, 0,0,0,0,0,0)
+ XTREG(122,488,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7, 0,0,0,0,0,0)
+ XTREG(123,492,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0)
+ XTREG(124,496,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0)
+ XTREG(125,500,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0)
+ XTREG(126,504,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0)
+ XTREG(127,508,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, 0,0,0,0,0,0)
+ XTREG(128,512,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, 0,0,0,0,0,0)
+ XTREG(129,516,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7, 0,0,0,0,0,0)
+ XTREG(130,520,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0)
+ XTREG(131,524,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0)
+ XTREG(132,528,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0)
+ XTREG(133,532,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0)
+ XTREG(134,536,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, 0,0,0,0,0,0)
+ XTREG(135,540,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, 0,0,0,0,0,0)
+ XTREG(136,544,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7, 0,0,0,0,0,0)
+ XTREG(137,548, 8, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable, 0,0,0,0,0,0)
+ XTREG(138,552,32, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0)
+ XTREG(139,556,32, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0)
+ XTREG(140,560,32, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0)
+ XTREG(141,564,32, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0)
+ XTREG(142,568,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
+ XTREG(143,572, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0)
+ XTREG(144,576,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0)
+ XTREG(145,580,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0)
+ XTREG(146,584,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0)
+ XTREG(147,588,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0)
+ XTREG(148,592, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0)
+ XTREG(149,596,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0)
+ XTREG(150,600,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0)
+ XTREG(151,604,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0)
+ XTREG(152,608,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2, 0,0,0,0,0,0)
+ XTREG(153,612,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0)
+ XTREG(154,616,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0)
+ XTREG(155,620,32, 4, 4,0x02f6,0x0007,-2, 2,0x1000,misc2, 0,0,0,0,0,0)
+ XTREG(156,624,32, 4, 4,0x02f7,0x0007,-2, 2,0x1000,misc3, 0,0,0,0,0,0)
+ XTREG(157,628,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0)
+ XTREG(158,632,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0)
+ XTREG(159,636,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0)
+ XTREG(160,640,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0)
+ XTREG(161,644,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0)
+ XTREG(162,648,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0)
+ XTREG(163,652,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0)
+ XTREG(164,656,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0)
+ XTREG(165,660,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0)
+ XTREG(166,664,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0)
+ XTREG(167,668,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, 0,0,0,0,0,0)
+ XTREG(168,672,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, 0,0,0,0,0,0)
+ XTREG(169,676,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, 0,0,0,0,0,0)
+ XTREG(170,680,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0)
+ XTREG(171,684,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0)
+ XTREG(172,688,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0)
+ XTREG(173,692, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0,
0,0,&xtensa_mask0,0,0,0)
- XTREG(114,456, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum,
+ XTREG(174,693, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1,
0,0,&xtensa_mask1,0,0,0)
- XTREG(115,460, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe,
+ XTREG(175,694, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2,
0,0,&xtensa_mask2,0,0,0)
- XTREG(116,464, 2, 4, 4,0x200b,0x0006,-2, 6,0x1010,psring,
+ XTREG(176,695, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3,
0,0,&xtensa_mask3,0,0,0)
- XTREG(117,468, 1, 4, 4,0x200c,0x0006,-2, 6,0x1010,psexcm,
+ XTREG(177,696, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4,
0,0,&xtensa_mask4,0,0,0)
- XTREG(118,472, 2, 4, 4,0x200d,0x0006,-2, 6,0x1010,pscallinc,
+ XTREG(178,697, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5,
0,0,&xtensa_mask5,0,0,0)
- XTREG(119,476, 4, 4, 4,0x200e,0x0006,-2, 6,0x1010,psowb,
+ XTREG(179,698, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6,
0,0,&xtensa_mask6,0,0,0)
- XTREG(120,480,20, 4, 4,0x200f,0x0006,-2, 6,0x1010,litbaddr,
+ XTREG(180,699, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7,
0,0,&xtensa_mask7,0,0,0)
- XTREG(121,484, 1, 4, 4,0x2010,0x0006,-2, 6,0x1010,litben,
+ XTREG(181,700, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8,
0,0,&xtensa_mask8,0,0,0)
- XTREG(122,488, 4, 4, 4,0x2015,0x0006,-2, 6,0x1010,dbnum,
+ XTREG(182,701, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9,
0,0,&xtensa_mask9,0,0,0)
- XTREG(123,492, 8, 4, 4,0x2016,0x0006,-2, 6,0x1010,asid3,
+ XTREG(183,702, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10,
0,0,&xtensa_mask10,0,0,0)
- XTREG(124,496, 8, 4, 4,0x2017,0x0006,-2, 6,0x1010,asid2,
+ XTREG(184,703, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11,
0,0,&xtensa_mask11,0,0,0)
- XTREG(125,500, 8, 4, 4,0x2018,0x0006,-2, 6,0x1010,asid1,
+ XTREG(185,704, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12,
0,0,&xtensa_mask12,0,0,0)
- XTREG(126,504, 2, 4, 4,0x2019,0x0006,-2, 6,0x1010,instpgszid4,
+ XTREG(186,705, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13,
0,0,&xtensa_mask13,0,0,0)
- XTREG(127,508, 2, 4, 4,0x201a,0x0006,-2, 6,0x1010,datapgszid4,
+ XTREG(187,706, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14,
0,0,&xtensa_mask14,0,0,0)
- XTREG(128,512,10, 4, 4,0x201b,0x0006,-2, 6,0x1010,ptbase,
+ XTREG(188,707, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15,
0,0,&xtensa_mask15,0,0,0)
+ XTREG(189,708, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel,
+ 0,0,&xtensa_mask16,0,0,0)
+ XTREG(190,712, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum,
+ 0,0,&xtensa_mask17,0,0,0)
+ XTREG(191,716, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe,
+ 0,0,&xtensa_mask18,0,0,0)
+ XTREG(192,720, 1, 4, 4,0x200b,0x0006,-2, 6,0x1010,psexcm,
+ 0,0,&xtensa_mask19,0,0,0)
+ XTREG(193,724, 2, 4, 4,0x200c,0x0006,-2, 6,0x1010,pscallinc,
+ 0,0,&xtensa_mask20,0,0,0)
+ XTREG(194,728, 4, 4, 4,0x200d,0x0006,-2, 6,0x1010,psowb,
+ 0,0,&xtensa_mask21,0,0,0)
+ XTREG(195,732,40, 8, 4,0x200e,0x0006,-2, 6,0x1010,acc,
+ 0,0,&xtensa_mask22,0,0,0)
+ XTREG(196,740, 4, 4, 4,0x2013,0x0006,-2, 6,0x1010,dbnum,
+ 0,0,&xtensa_mask23,0,0,0)
+ XTREG(197,744,64, 8, 4,0x2015,0x0006,-2, 5,0x1010,f64r,
+ 0,0,&xtensa_mask24,0,0,0)
+ XTREG(198,752, 2, 4, 4,0x2016,0x0006, 0, 5,0x1010,roundmode,
+ 0,0,&xtensa_mask25,0,0,0)
+ XTREG(199,756, 1, 4, 4,0x2017,0x0006, 0, 5,0x1010,invalidenable,
+ 0,0,&xtensa_mask26,0,0,0)
+ XTREG(200,760, 1, 4, 4,0x2018,0x0006, 0, 5,0x1010,divzeroenable,
+ 0,0,&xtensa_mask27,0,0,0)
+ XTREG(201,764, 1, 4, 4,0x2019,0x0006, 0, 5,0x1010,overflowenable,
+ 0,0,&xtensa_mask28,0,0,0)
+ XTREG(202,768, 1, 4, 4,0x201a,0x0006, 0, 5,0x1010,underflowenable,
+ 0,0,&xtensa_mask29,0,0,0)
+ XTREG(203,772, 1, 4, 4,0x201b,0x0006, 0, 5,0x1010,inexactenable,
+ 0,0,&xtensa_mask30,0,0,0)
+ XTREG(204,776, 1, 4, 4,0x201c,0x0006, 0, 5,0x1010,invalidflag,
+ 0,0,&xtensa_mask31,0,0,0)
+ XTREG(205,780, 1, 4, 4,0x201d,0x0006, 0, 5,0x1010,divzeroflag,
+ 0,0,&xtensa_mask32,0,0,0)
+ XTREG(206,784, 1, 4, 4,0x201e,0x0006, 0, 5,0x1010,overflowflag,
+ 0,0,&xtensa_mask33,0,0,0)
+ XTREG(207,788, 1, 4, 4,0x201f,0x0006, 0, 5,0x1010,underflowflag,
+ 0,0,&xtensa_mask34,0,0,0)
+ XTREG(208,792, 1, 4, 4,0x2020,0x0006, 0, 5,0x1010,inexactflag,
+ 0,0,&xtensa_mask35,0,0,0)
+ XTREG(209,796,20, 4, 4,0x2021,0x0006, 0, 5,0x1010,fpreserved20,
+ 0,0,&xtensa_mask36,0,0,0)
+ XTREG(210,800,20, 4, 4,0x2022,0x0006, 0, 5,0x1010,fpreserved20a,
+ 0,0,&xtensa_mask37,0,0,0)
+ XTREG(211,804, 5, 4, 4,0x2023,0x0006, 0, 5,0x1010,fpreserved5,
+ 0,0,&xtensa_mask38,0,0,0)
XTREG_END
};
#ifdef XTENSA_CONFIG_INSTANTIATE
-XTENSA_CONFIG_INSTANTIATE(rmap,0)
+XTENSA_CONFIG_INSTANTIATE(rmap,4)
#endif

105
devel/xtensa-esp32-elf/gdb/patches/patch-gdb_xtensa-xtregs_c Normal file
View file

@ -0,0 +1,105 @@
File from espressif overlays.
Index: gdb/xtensa-xtregs.c
--- gdb/xtensa-xtregs.c.orig
+++ gdb/xtensa-xtregs.c
@@ -1,39 +1,71 @@
-/* Table mapping between kernel xtregset and GDB register cache.
- Copyright (C) 2007-2020 Free Software Foundation, Inc.
+/* Customized table mapping between kernel xtregset and GDB register cache.
- This file is part of GDB.
+ Copyright (c) 2007-2010 Tensilica Inc.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 3 of the
- License, or (at your option) any later version.
+ Permission is hereby granted, free of charge, to any person obtaining
+ a copy of this software and associated documentation files (the
+ "Software"), to deal in the Software without restriction, including
+ without limitation the rights to use, copy, modify, merge, publish,
+ distribute, sublicense, and/or sell copies of the Software, and to
+ permit persons to whom the Software is furnished to do so, subject to
+ the following conditions:
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- General Public License for more details.
+ The above copyright notice and this permission notice shall be included
+ in all copies or substantial portions of the Software.
- You should have received a copy of the GNU General Public License
- along with this program. If not, see <http://www.gnu.org/licenses/>. */
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-typedef struct
-{
- int gdb_regnum;
- int gdb_offset;
- int ptrace_cp_offset;
- int ptrace_offset;
- int size;
- int coproc;
- int dbnum;
- const char *name;
-} xtensa_regtable_t;
+typedef struct {
+ int gdb_regnum;
+ int gdb_offset;
+ int ptrace_cp_offset;
+ int ptrace_offset;
+ int size;
+ int coproc;
+ int dbnum;
+ char* name
+;} xtensa_regtable_t;
-#define XTENSA_ELF_XTREG_SIZE 4
+#define XTENSA_ELF_XTREG_SIZE 116
-const xtensa_regtable_t xtensa_regmap_table[] =
-{
+const xtensa_regtable_t xtensa_regmap_table[] = {
/* gnum,gofs,cpofs,ofs,siz,cp, dbnum, name */
- { 44, 176, 0, 0, 4, -1, 0x020c, "scompare1" },
+ { 75, 300, 8, 8, 4, -1, 0x0204, "br" },
+ { 76, 304, 12, 12, 4, -1, 0x020c, "scompare1" },
+ { 77, 308, 0, 0, 4, -1, 0x0210, "acclo" },
+ { 78, 312, 4, 4, 4, -1, 0x0211, "acchi" },
+ { 79, 316, 16, 16, 4, -1, 0x0220, "m0" },
+ { 80, 320, 20, 20, 4, -1, 0x0221, "m1" },
+ { 81, 324, 24, 24, 4, -1, 0x0222, "m2" },
+ { 82, 328, 28, 28, 4, -1, 0x0223, "m3" },
+ { 84, 336, 32, 32, 4, -1, 0x03ea, "f64r_lo" },
+ { 85, 340, 36, 36, 4, -1, 0x03eb, "f64r_hi" },
+ { 86, 344, 40, 40, 4, -1, 0x03ec, "f64s" },
+ { 87, 348, 8, 52, 4, 0, 0x0030, "f0" },
+ { 88, 352, 12, 56, 4, 0, 0x0031, "f1" },
+ { 89, 356, 16, 60, 4, 0, 0x0032, "f2" },
+ { 90, 360, 20, 64, 4, 0, 0x0033, "f3" },
+ { 91, 364, 24, 68, 4, 0, 0x0034, "f4" },
+ { 92, 368, 28, 72, 4, 0, 0x0035, "f5" },
+ { 93, 372, 32, 76, 4, 0, 0x0036, "f6" },
+ { 94, 376, 36, 80, 4, 0, 0x0037, "f7" },
+ { 95, 380, 40, 84, 4, 0, 0x0038, "f8" },
+ { 96, 384, 44, 88, 4, 0, 0x0039, "f9" },
+ { 97, 388, 48, 92, 4, 0, 0x003a, "f10" },
+ { 98, 392, 52, 96, 4, 0, 0x003b, "f11" },
+ { 99, 396, 56, 100, 4, 0, 0x003c, "f12" },
+ { 100, 400, 60, 104, 4, 0, 0x003d, "f13" },
+ { 101, 404, 64, 108, 4, 0, 0x003e, "f14" },
+ { 102, 408, 68, 112, 4, 0, 0x003f, "f15" },
+ { 103, 412, 0, 44, 4, 0, 0x03e8, "fcr" },
+ { 104, 416, 4, 48, 4, 0, 0x03e9, "fsr" },
{ 0 }
};
+

147
devel/xtensa-esp32-elf/gdb/patches/patch-include_xtensa-config_h Normal file
View file

@ -0,0 +1,147 @@
xtensa-config.h file for ESP32
Index: include/xtensa-config.h
--- include/xtensa-config.h.orig
+++ include/xtensa-config.h
@@ -1,5 +1,6 @@
/* Xtensa configuration settings.
- Copyright (C) 2001-2019 Free Software Foundation, Inc.
+ Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
+ Free Software Foundation, Inc.
Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica.
This program is free software; you can redistribute it and/or modify
@@ -25,7 +26,7 @@
macros. */
#undef XCHAL_HAVE_BE
-#define XCHAL_HAVE_BE 1
+#define XCHAL_HAVE_BE 0
#undef XCHAL_HAVE_DENSITY
#define XCHAL_HAVE_DENSITY 1
@@ -49,7 +50,7 @@
#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */
#undef XCHAL_HAVE_MAC16
-#define XCHAL_HAVE_MAC16 0
+#define XCHAL_HAVE_MAC16 1
#undef XCHAL_HAVE_MUL16
#define XCHAL_HAVE_MUL16 1
@@ -58,7 +59,7 @@
#define XCHAL_HAVE_MUL32 1
#undef XCHAL_HAVE_MUL32_HIGH
-#define XCHAL_HAVE_MUL32_HIGH 0
+#define XCHAL_HAVE_MUL32_HIGH 1
#undef XCHAL_HAVE_DIV32
#define XCHAL_HAVE_DIV32 1
@@ -85,30 +86,37 @@
#define XCHAL_HAVE_S32C1I 1
#undef XCHAL_HAVE_BOOLEANS
-#define XCHAL_HAVE_BOOLEANS 0
+#define XCHAL_HAVE_BOOLEANS 1
#undef XCHAL_HAVE_FP
-#define XCHAL_HAVE_FP 0
+#define XCHAL_HAVE_FP 1
#undef XCHAL_HAVE_FP_DIV
-#define XCHAL_HAVE_FP_DIV 0
+#define XCHAL_HAVE_FP_DIV 1
#undef XCHAL_HAVE_FP_RECIP
-#define XCHAL_HAVE_FP_RECIP 0
+#define XCHAL_HAVE_FP_RECIP 1
#undef XCHAL_HAVE_FP_SQRT
-#define XCHAL_HAVE_FP_SQRT 0
+#define XCHAL_HAVE_FP_SQRT 1
#undef XCHAL_HAVE_FP_RSQRT
-#define XCHAL_HAVE_FP_RSQRT 0
+#define XCHAL_HAVE_FP_RSQRT 1
+#undef XCHAL_HAVE_FP_POSTINC
+#define XCHAL_HAVE_FP_POSTINC 1
+
+#undef XCHAL_HAVE_DFP_ACCEL
+#define XCHAL_HAVE_DFP_ACCEL 1
+/* For backward compatibility */
#undef XCHAL_HAVE_DFP_accel
-#define XCHAL_HAVE_DFP_accel 0
+#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL
+
#undef XCHAL_HAVE_WINDOWED
#define XCHAL_HAVE_WINDOWED 1
#undef XCHAL_NUM_AREGS
-#define XCHAL_NUM_AREGS 32
+#define XCHAL_NUM_AREGS 64
#undef XCHAL_HAVE_WIDE_BRANCHES
#define XCHAL_HAVE_WIDE_BRANCHES 0
@@ -118,34 +126,31 @@
#undef XCHAL_ICACHE_SIZE
-#define XCHAL_ICACHE_SIZE 16384
+#define XCHAL_ICACHE_SIZE 0
#undef XCHAL_DCACHE_SIZE
-#define XCHAL_DCACHE_SIZE 16384
+#define XCHAL_DCACHE_SIZE 0
#undef XCHAL_ICACHE_LINESIZE
-#define XCHAL_ICACHE_LINESIZE 32
+#define XCHAL_ICACHE_LINESIZE 16
#undef XCHAL_DCACHE_LINESIZE
-#define XCHAL_DCACHE_LINESIZE 32
+#define XCHAL_DCACHE_LINESIZE 16
#undef XCHAL_ICACHE_LINEWIDTH
-#define XCHAL_ICACHE_LINEWIDTH 5
+#define XCHAL_ICACHE_LINEWIDTH 4
#undef XCHAL_DCACHE_LINEWIDTH
-#define XCHAL_DCACHE_LINEWIDTH 5
+#define XCHAL_DCACHE_LINEWIDTH 4
#undef XCHAL_DCACHE_IS_WRITEBACK
-#define XCHAL_DCACHE_IS_WRITEBACK 1
+#define XCHAL_DCACHE_IS_WRITEBACK 0
#undef XCHAL_HAVE_MMU
-#define XCHAL_HAVE_MMU 1
+#define XCHAL_HAVE_MMU 0
-#undef XCHAL_MMU_MIN_PTE_PAGE_SIZE
-#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12
-
#undef XCHAL_HAVE_DEBUG
#define XCHAL_HAVE_DEBUG 1
@@ -172,5 +177,16 @@
#define XSHAL_ABI XTHAL_ABI_WINDOWED
#define XTHAL_ABI_WINDOWED 0
#define XTHAL_ABI_CALL0 1
+
+
+#undef XCHAL_M_STAGE
+#define XCHAL_M_STAGE 3
+
+#undef XTENSA_MARCH_LATEST
+#define XTENSA_MARCH_LATEST 260003
+
+#undef XTENSA_MARCH_EARLIEST
+#define XTENSA_MARCH_EARLIEST 260003
+
#endif /* !XTENSA_CONFIG_H */

1
devel/xtensa-esp32-elf/gdb/pkg/DESCR Normal file
View file

@ -0,0 +1 @@
GNU debugger, configured for the xtensa-esp32-elf target.

38
devel/xtensa-esp32-elf/gdb/pkg/PLIST Normal file
View file

@ -0,0 +1,38 @@
@bin xtensa-esp32-elf/bin/xtensa-esp32-elf-gdb
xtensa-esp32-elf/bin/xtensa-esp32-elf-gdb-add-index
xtensa-esp32-elf/include/
xtensa-esp32-elf/include/gdb/
xtensa-esp32-elf/include/gdb/jit-reader.h
xtensa-esp32-elf/lib/charset.alias
xtensa-esp32-elf/share/gdb/
xtensa-esp32-elf/share/gdb/syscalls/
xtensa-esp32-elf/share/gdb/syscalls/aarch64-linux.xml
xtensa-esp32-elf/share/gdb/syscalls/amd64-linux.xml
xtensa-esp32-elf/share/gdb/syscalls/arm-linux.xml
xtensa-esp32-elf/share/gdb/syscalls/freebsd.xml
xtensa-esp32-elf/share/gdb/syscalls/gdb-syscalls.dtd
xtensa-esp32-elf/share/gdb/syscalls/i386-linux.xml
xtensa-esp32-elf/share/gdb/syscalls/mips-n32-linux.xml
xtensa-esp32-elf/share/gdb/syscalls/mips-n64-linux.xml
xtensa-esp32-elf/share/gdb/syscalls/mips-o32-linux.xml
xtensa-esp32-elf/share/gdb/syscalls/ppc-linux.xml
xtensa-esp32-elf/share/gdb/syscalls/ppc64-linux.xml
xtensa-esp32-elf/share/gdb/syscalls/s390-linux.xml
xtensa-esp32-elf/share/gdb/syscalls/s390x-linux.xml
xtensa-esp32-elf/share/gdb/syscalls/sparc-linux.xml
xtensa-esp32-elf/share/gdb/syscalls/sparc64-linux.xml
xtensa-esp32-elf/share/gdb/system-gdbinit/
xtensa-esp32-elf/share/gdb/system-gdbinit/elinos.py
xtensa-esp32-elf/share/gdb/system-gdbinit/wrs-linux.py
@info xtensa-esp32-elf/share/info/
@info xtensa-esp32-elf/share/info/annotate.info
@comment @info xtensa-esp32-elf/share/info/bfd.info
@info xtensa-esp32-elf/share/info/gdb.info
@info xtensa-esp32-elf/share/info/stabs.info
@man xtensa-esp32-elf/share/man/man1/xtensa-esp32-elf-gdb-add-index.1
@man xtensa-esp32-elf/share/man/man1/xtensa-esp32-elf-gdb.1
@man xtensa-esp32-elf/share/man/man1/xtensa-esp32-elf-gdbserver.1
xtensa-esp32-elf/share/man/man5/
@man xtensa-esp32-elf/share/man/man5/xtensa-esp32-elf-gdbinit.5
xtensa-esp32-elf/xtensa-esp32-elf/lib/
@static-lib xtensa-esp32-elf/xtensa-esp32-elf/lib/libiberty.a