SecBSD's official ports repository

2023-08-16 22:26:55 +00:00 · 2023-08-16 22:26:55 +00:00 · 2c0afcbbf3
commit 2c0afcbbf3
64331 changed files with 5339189 additions and 0 deletions
--- a/devel/clang-tools-extra/patches/patch-lib_Target_Mips_MipsFrameLowering_cpp
+++ b/devel/clang-tools-extra/patches/patch-lib_Target_Mips_MipsFrameLowering_cpp
@ -0,0 +1,33 @@
+Add retguard for octeon/mips64.
+
+Index: lib/Target/Mips/MipsFrameLowering.cpp
+--- lib/Target/Mips/MipsFrameLowering.cpp.orig
+++ lib/Target/Mips/MipsFrameLowering.cpp
+@@ -14,6 +14,7 @@
+ #include "MCTargetDesc/MipsBaseInfo.h"
+ #include "MipsInstrInfo.h"
+ #include "MipsMachineFunction.h"
+#include "MipsReturnProtectorLowering.h"
+ #include "MipsTargetMachine.h"
+ #include "llvm/CodeGen/MachineFrameInfo.h"
+ #include "llvm/CodeGen/MachineFunction.h"
+@@ -122,6 +123,10 @@ uint64_t MipsFrameLowering::estimateStackSize(const Ma
+     if (MFI.getObjectOffset(I) > 0)
+       Size += MFI.getObjectSize(I);
+ 
+  // Account for saving return protector register
+  if (MFI.getReturnProtectorNeeded())
+    Size += TRI.getSpillSize(*TRI.getMinimalPhysRegClass(Mips::T9_64));
+
+   // Conservatively assume all callee-saved registers will be saved.
+   for (const MCPhysReg *R = TRI.getCalleeSavedRegs(&MF); *R; ++R) {
+     unsigned RegSize = TRI.getSpillSize(*TRI.getMinimalPhysRegClass(*R));
+@@ -148,4 +153,8 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, Mac
+   }
+ 
+   return MBB.erase(I);
+}
+
+const ReturnProtectorLowering *MipsFrameLowering::getReturnProtector() const {
+  return &RPL;
+ }