31 lines
576 B
Makefile
31 lines
576 B
Makefile
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COMMENT= very fast free Verilog HDL simulator
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DISTNAME = verilator-3.912
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CATEGORIES= lang devel
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REVISION = 3
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HOMEPAGE= https://www.veripool.org/wiki/verilator/Intro
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# LGPLv3 or Perl
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PERMIT_PACKAGE= Yes
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MASTER_SITES= https://www.veripool.org/ftp/
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EXTRACT_SUFX= .tgz
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WANTLIB= c m ${COMPILER_LIBCXX}
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COMPILER = base-clang ports-gcc base-gcc
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BUILD_DEPENDS += devel/bison
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CONFIGURE_STYLE= gnu
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MAKE_FLAGS= VERILATOR_ROOT=${PREFIX}/share/verilator/ \
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COPT="${CFLAGS}"
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USE_GMAKE= Yes
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TEST_TARGET= test
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TEST_FLAGS= VERILATOR_ROOT=${WRKSRC}
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.include <bsd.port.mk>
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