ports/security/rust-ring/patches/patch-pregenerated_p256-x86_64-asm-elf_S

Index: pregenerated/p256-x86_64-asm-elf.S
--- pregenerated/p256-x86_64-asm-elf.S.orig
+++ pregenerated/p256-x86_64-asm-elf.S
@@ -1,6 +1,12 @@
 # This file is generated from a similarly-named Perl script in the BoringSSL
 # source tree. Do not edit by hand.
 
+#if defined(__CET__)
+#include <cet.h>
+#else
+#define _CET_ENDBR
+#endif
+
 #if defined(__has_feature)
 #if __has_feature(memory_sanitizer) && !defined(OPENSSL_NO_ASM)
 #define OPENSSL_NO_ASM
@@ -12,7 +18,7 @@
 .extern	GFp_ia32cap_P
 .hidden GFp_ia32cap_P
 
-
+.section .rodata
 .align	64
 .Lpoly:
 .quad	0xffffffffffffffff, 0x00000000ffffffff, 0x0000000000000000, 0xffffffff00000001
@@ -31,14 +37,15 @@
 .quad	0xf3b9cac2fc632551, 0xbce6faada7179e84, 0xffffffffffffffff, 0xffffffff00000000
 .LordK:
 .quad	0xccd1c8aaee00bc4f
+.text
 
 
-
 .globl	GFp_nistz256_add
 .hidden GFp_nistz256_add
 .type	GFp_nistz256_add,@function
 .align	32
 GFp_nistz256_add:
+	_CET_ENDBR
 	pushq	%r12
 	pushq	%r13
 
@@ -87,6 +94,7 @@ GFp_nistz256_add:
 .align	32
 GFp_nistz256_neg:
 .cfi_startproc	
+	_CET_ENDBR
 	pushq	%r12
 .cfi_adjust_cfa_offset	8
 .cfi_offset	%r12,-16
@@ -149,6 +157,7 @@ GFp_nistz256_neg:
 .align	32
 GFp_p256_scalar_mul_mont:
 .cfi_startproc	
+	_CET_ENDBR
 	leaq	GFp_ia32cap_P(%rip),%rcx
 	movq	8(%rcx),%rcx
 	andl	$0x80100,%ecx
@@ -483,6 +492,7 @@ GFp_p256_scalar_mul_mont:
 .align	32
 GFp_p256_scalar_sqr_rep_mont:
 .cfi_startproc	
+	_CET_ENDBR
 	leaq	GFp_ia32cap_P(%rip),%rcx
 	movq	8(%rcx),%rcx
 	andl	$0x80100,%ecx
@@ -1242,6 +1252,7 @@ ecp_nistz256_ord_sqr_montx:
 .align	32
 GFp_nistz256_mul_mont:
 .cfi_startproc	
+	_CET_ENDBR
 	leaq	GFp_ia32cap_P(%rip),%rcx
 	movq	8(%rcx),%rcx
 	andl	$0x80100,%ecx
@@ -1539,6 +1550,7 @@ __ecp_nistz256_mul_montq:
 .align	32
 GFp_nistz256_sqr_mont:
 .cfi_startproc	
+	_CET_ENDBR
 	leaq	GFp_ia32cap_P(%rip),%rcx
 	movq	8(%rcx),%rcx
 	andl	$0x80100,%ecx
@@ -2069,6 +2081,7 @@ __ecp_nistz256_sqr_montx:
 .align	32
 GFp_nistz256_select_w5:
 .cfi_startproc	
+	_CET_ENDBR
 	leaq	GFp_ia32cap_P(%rip),%rax
 	movq	8(%rax),%rax
 	testl	$32,%eax
@@ -2136,6 +2149,7 @@ GFp_nistz256_select_w5:
 .align	32
 GFp_nistz256_select_w7:
 .cfi_startproc	
+	_CET_ENDBR
 	leaq	GFp_ia32cap_P(%rip),%rax
 	movq	8(%rax),%rax
 	testl	$32,%eax
@@ -2255,6 +2269,7 @@ GFp_nistz256_avx2_select_w5:
 .align	32
 GFp_nistz256_avx2_select_w7:
 .cfi_startproc	
+	_CET_ENDBR
 .Lavx2_select_w7:
 	vzeroupper
 	vmovdqa	.LThree(%rip),%ymm0
@@ -2462,6 +2477,7 @@ __ecp_nistz256_mul_by_2q:
 .align	32
 GFp_nistz256_point_double:
 .cfi_startproc	
+	_CET_ENDBR
 	leaq	GFp_ia32cap_P(%rip),%rcx
 	movq	8(%rcx),%rcx
 	andl	$0x80100,%ecx
@@ -2696,6 +2712,7 @@ GFp_nistz256_point_double:
 .align	32
 GFp_nistz256_point_add:
 .cfi_startproc	
+	_CET_ENDBR
 	leaq	GFp_ia32cap_P(%rip),%rcx
 	movq	8(%rcx),%rcx
 	andl	$0x80100,%ecx
@@ -3133,6 +3150,7 @@ GFp_nistz256_point_add:
 .align	32
 GFp_nistz256_point_add_affine:
 .cfi_startproc	
+	_CET_ENDBR
 	leaq	GFp_ia32cap_P(%rip),%rcx
 	movq	8(%rcx),%rcx
 	andl	$0x80100,%ecx